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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260921
DTEND;VALUE=DATE:20260923
DTSTAMP:20260923T100010
CREATED:20260520T090952Z
LAST-MODIFIED:20260520T090952Z
UID:2356-1789948800-1790121599@czechsemiconductorcentre.cz
SUMMARY:FD-SOI ICs Design Opportunities Short Course
DESCRIPTION:The FAMES Pilot Line informs that pre-registrations is still open for the FD-SOI ICs Design Opportunities Short Course. taking place in: \nDate: 21–22 September 2026\nGrenoble\, France \nThis one-and-a-half-day training\, provided by FD-SOI experts\, will provide a comprehensive overview of FD-SOI technology and advanced design methodologies for digital\, analog\, RF and power management circuits. It is aimed for engineers\, researchers and technologists interested in leveraging FD-SOI for next-generation integrated circuits. \nThe program also includes technical tutorials\, networking opportunities and an immersive clean-room visit at CEA-Leti. \nConsult the full program and pre-register here: https://fames-pilot-line.eu/fd-soi-ics-design-opportunities-short-course/. \n⚠️This is a paid event with limited capacity.
URL:https://czechsemiconductorcentre.cz/event/fd-soi-ics-design-opportunities-short-course/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/FD-SOI_ics_Grenoble.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260914
DTEND;VALUE=DATE:20260919
DTSTAMP:20260923T100010
CREATED:20260701T134537Z
LAST-MODIFIED:20260701T134537Z
UID:2508-1789344000-1789775999@czechsemiconductorcentre.cz
SUMMARY:ECCE Europe 2026 in Valencia
DESCRIPTION:ECCE Europe is Europe’s leading conference on power electronics and energy conversion\, bringing together researchers\, industry experts\, and innovators from around the world. It will be taking place from 14 – 18 September 2026 in Valencia\, Spain. \nThe ECCE Europe 2026 conference and exhibition will take place from 14 – 18 September at the Valencia Conference Center in Valencia\, Spain. \nCommencing in 2024\, IEEE PELS is embarking on a dynamic new collaboration with the European Center for Power Electronics (ECPE) for the PELS flagship conference\, now titled IEEE ECCE Europe. United\, IEEE PELS and ECPE are on the brink of unprecedented opportunities in Europe: nurturing innovation\, facilitating the exchange of knowledge\, and catalyzing transformative breakthroughs in the realm of global power electronics. IEEE PELS and ECPE are inviting the Power Electronics community from academia and industry in Europe to follow us in shaping the new ECCE Europe Conference. \nConference Highlights: \n\nCutting-edge Research Presentations\nKeynote Speakers & Industry Experts\nIndustry Sessions\nDiverse Technical Tracks\nWorkshops and Tutorials\nNetworking Opportunities\nStudent Job Fairs
URL:https://czechsemiconductorcentre.cz/event/ecce-europe-2026-in-valencia/
LOCATION:Valencia\, Valencia\, Spain
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/07/x.webp
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260914
DTEND;VALUE=DATE:20260917
DTSTAMP:20260923T100010
CREATED:20260729T123453Z
LAST-MODIFIED:20260729T123453Z
UID:2590-1789344000-1789603199@czechsemiconductorcentre.cz
SUMMARY:ISIG Executive Summit EU 2026
DESCRIPTION:Prague will welcome senior representatives of the global semiconductor industry on 14–16 September 2026. The ISIG Executive Summit EU will bring together decision-makers from the semiconductor\, power electronics and advanced manufacturing sectors to discuss the technologies and strategic choices shaping Europe’s industrial future. \nHeld under the theme “Chips\, Power and Machines: Powering AI and Electrifying Industry”\, the summit will connect international industry leaders\, technology experts\, investors and policymakers with Czechia’s rapidly developing semiconductor ecosystem. \nThe programme will explore some of the most important trends affecting the industry\, including Europe’s future position in the global semiconductor market\, the development of the European Chips Act\, advanced manufacturing\, artificial intelligence\, robotics and the electrification of transport and industry. \nFrom power electronics to intelligent machines\nA major focus of the event will be on the technologies enabling the next generation of electric vehicles and industrial systems. Participants will examine how 800-volt architectures and power semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) can improve performance\, energy efficiency\, charging speed and reliability. \nFurther sessions will address the semiconductor requirements of humanoid robots and autonomous systems\, including edge intelligence\, real-time decision-making\, advanced sensing and energy-efficient computing. \nThe agenda will also cover: \n\nadvanced processes\, materials and testing for scalable SiC and GaN production;\nautomation and data-driven optimisation in intelligent semiconductor fabs;\nfunding opportunities for innovative and scalable semiconductor projects;\nthe future of wide-bandgap semiconductor research and development;\nthe impact of artificial intelligence and the emerging Chips Act 2.0 on the power\, automotive and industrial sectors;\nthe capabilities and future development of the Czech semiconductor industry.\n\nInternational speakers and Czech expertise\nThe summit will feature senior representatives of leading global semiconductor companies. Confirmed speakers include Thomas Morgenstern\, Executive Vice President for Manufacturing at STMicroelectronics\, and Magdalena Christine Böbel\, Executive Vice President for Integrated Circuits for Energy Systems and Head of the corresponding business division at Infineon Technologies. \nThe programme will also introduce international participants to Czechia’s semiconductor expertise\, industrial capabilities and potential for deeper integration into European and global value chains. \nAs part of the summit\, delegates will have an opportunity to visit the Hitachi Energy Semiconductors facility in Prague\, providing a first-hand look at semiconductor production and expertise based in Czechia. \nThe event is supported by CzechInvest in cooperation with the Ministry of Foreign Affairs of the Czech Republic. \nEvent details\nEvent: ISIG Executive Summit EU 2026\nDate: 14–16 September 2026\nLocation: Prague\, Czechia\nMain theme: Chips\, Power and Machines: Powering AI and Electrifying Industry\nLanguage: English \nJoin semiconductor executives\, technology leaders\, investors and policymakers in Prague and take part in the discussion about the future of chips\, power electronics\, artificial intelligence and advanced industrial manufacturing in Europe. \nRegister on the official ISIG Executive Summit EU website.
URL:https://czechsemiconductorcentre.cz/event/isig-executive-summit-eu-2026/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/07/ISIG_banner_1.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260903T093000
DTEND;TZID=Europe/Prague:20260903T143000
DTSTAMP:20260923T100010
CREATED:20260827T090246Z
LAST-MODIFIED:20260827T090734Z
UID:2644-1788427800-1788445800@czechsemiconductorcentre.cz
SUMMARY:Industrial Property Workshop
DESCRIPTION:Protect Your Innovation: Industrial Property Workshop (not only) for Semiconductor Companies\n3 September 2026 | 9:30–14:30 | Moravian Library\, Brno \nPatents and intellectual property are a fundamental part of the semiconductor business. From chip architectures and circuit designs to manufacturing technologies\, materials\, equipment and applications\, companies need to understand not only how to protect their own innovations\, but also how to navigate existing intellectual property rights. \nLarge semiconductor companies typically have dedicated IP teams\, patent specialists and established procedures for training R&D staff. Start-ups\, SMEs and smaller technology companies face many of the same challenges – often without comparable in-house resources. For them\, a practical understanding of industrial property can therefore be particularly valuable. \nThe Moravian Library in Brno is hosting a free workshop\, Introduction to Industrial Property Rights and Databases of the Industrial Property Office of the Czech Republic\, on 3 September. Participants will receive an introduction to patents\, utility models\, industrial designs\, trade marks and other forms of industrial property protection. The programme will also include practical exercises in searching freely accessible databases of the Czech Industrial Property Office. \nThe workshop will also introduce opportunities for financial support for industrial property protection through the Innovation Vouchers scheme. The programme will be led by Hana Churáčková from the Industrial Property Office of the Czech Republic and Hana Rozkopalová from the Business and Innovation Agency. \nFor semiconductor start-ups\, SMEs\, researchers and innovators\, the workshop offers an accessible opportunity to strengthen an area that can have a direct impact on a company’s technology strategy\, competitiveness and ability to commercialise R&D results. \nParticipation is free of charge\, but capacity is limited and advance registration is required.
URL:https://czechsemiconductorcentre.cz/event/industrial-property-workshop/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/08/a571d19b-1ae4-4a6e-aea5-d44fba840903.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260902T093000
DTEND;TZID=Europe/Prague:20260902T153000
DTSTAMP:20260923T100010
CREATED:20260729T124041Z
LAST-MODIFIED:20260729T124120Z
UID:2593-1788341400-1788363000@czechsemiconductorcentre.cz
SUMMARY:Inclusive Chips Forum Bratislava: Bridging Education and Industry for Diverse Talent
DESCRIPTION:How can universities\, employers and public institutions work together to open the semiconductor industry to a wider range of talent? The Inclusive Chips Forum Bratislava will bring together representatives of education\, industry and European initiatives on 2 September 2026 to share practical experience and discuss more inclusive pathways into semiconductor careers. \nThe event\, entitled Inclusive Chips Forum Bratislava: Bridging Education and Industry for Diverse Talent\, will take place at the Faculty of Electrical Engineering and Information Technology of the Slovak University of Technology in Bratislava. \nThe Czech Semiconductor Centre will be represented by Jana Drbohlavová\, Deputy Director of CSC\, who will join the panel discussion “Connecting Education and Industry to Build Diverse Semiconductor Talent”. \nBuilding stronger pathways into the semiconductor industry\nEurope’s semiconductor sector needs a growing number of skilled professionals. Meeting this demand will require not only the development of technical expertise\, but also broader access to education\, stronger cooperation between academia and employers\, and working environments in which people with different backgrounds and professional profiles can succeed. \nThe forum will explore how educational institutions and semiconductor employers can jointly attract\, develop and retain a more diverse talent pool. Discussions will focus on the role of university leadership and institutional culture\, barriers preventing people from entering semiconductor careers\, and successful approaches to connecting education with the rapidly changing needs of industry. \nDuring the afternoon panel\, Jana Drbohlavová will be joined by representatives of SEMI Europe\, the Slovak Ministry of Education\, Research\, Development and Youth\, and other participating organisations. The discussion will examine: \n\nhow diversity\, equity and inclusion initiatives can be embedded in education;\nhow universities and employers can cooperate more effectively;\nwhat prevents talented people from pursuing careers in semiconductors;\nwhich talent development models have proved successful;\nhow education can respond to the evolving requirements of the technology sector.\n\nEvent details\nEvent: Inclusive Chips Forum Bratislava: Bridging Education and Industry for Diverse Talent\nDate: 2 September 2026\nTime: 9.30 a.m.–3.30 p.m.\nVenue: Faculty of Electrical Engineering and Information Technology\, Slovak University of Technology in Bratislava\nAddress: Ilkovičova 3\, Bratislava\, Slovakia\nLanguages: Slovak and English\, with simultaneous interpretation \nParticipation is free of charge\, but prior registration is required. \nJoin the discussion in Bratislava and discover how stronger cooperation between education and industry can help Europe build a more inclusive\, skilled and resilient semiconductor workforce. \nLearn more\, view the full agenda and register on the Inclusive Chips Forum website.
URL:https://czechsemiconductorcentre.cz/event/inclusive-chips-forum-bratislava-bridging-education-and-industry-for-diverse-talent/
LOCATION:Bratislava\, Bratislava\, Slovakia (Slovak Republic)
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/07/Bratislava-Forum-banner.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260831
DTEND;VALUE=DATE:20260904
DTSTAMP:20260923T100010
CREATED:20250710T115052Z
LAST-MODIFIED:20250710T115052Z
UID:1537-1788134400-1788479999@czechsemiconductorcentre.cz
SUMMARY:NFO18 – Near-Field Optics\, Nanophotonics and Related Techniques Conference
DESCRIPTION:NFO18 – the 18th International Conference on Near-Field Optics\, Nanophotonics and Related Techniques \nFollowing NFO3 in 1995\, we are honored to host this prestigious event in Brno once again. Brno is an academic and technology hub\, home to several universities (with over 80\,000 students)\, research institutes and high-tech companies. Notably\, it hosts three major electron microscope manufacturers\, whose combined output accounts for about one-third of the world’s total production. This unique position makes our city an ideal venue for discussions on the latest advances in near-field optics and other related nanophotonic domains\, including novel materials\, and nanofabrication technologies. A special attention will be given to an emerging field combining near-field optical and electron-beam techniques.  \nThe NFO Summer School preceding the conference (August 30)\, will offer hands-on workshops\, specialized tutorials\, and valuable networking opportunities  for early-career researchers. NFO18 itself will bring together specialists from academia and industry to exchange ideas and foster collaborations in a welcoming\, focused environment.  \nPlease mark your calendars and stay tuned for details. Whether you seek cutting-edge knowledge\, new partnerships\, or simply want to experience Brno’s vibrant atmosphere\, we look forward to your participation.  \nNFO18 is organised by Brno University of Technology (Faculty of Mechanical Engineering and CEITEC BUT)
URL:https://czechsemiconductorcentre.cz/event/nfo18-near-field-optics-nanophotonics-and-related-techniques-conference/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/Snimek-obrazovky-2025-07-10-134831.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260829
DTEND;VALUE=DATE:20260906
DTSTAMP:20260923T100010
CREATED:20250918T124143Z
LAST-MODIFIED:20250918T124143Z
UID:1644-1787961600-1788652799@czechsemiconductorcentre.cz
SUMMARY:European Federation of Electron Paramagnetic Resonance (EFEPR)
DESCRIPTION:13th European Federation of Electron Paramagnetic Resonance (EFEPR) Conference\, taking place in Brno\, Czech Republic. This year\, we have prepared a rich and varied programme\, complemented by two additional days dedicated to the Young Researcher Conference (EFEPR). You can look forward to a diverse array of professional contributions\, the exchange of valuable experiences\, and opportunities for both formal discussions and informal networking. Beyond the academic programme\, you will also have the chance to enjoy the renowned hospitality and charm of the Brno region and the family-friendly atmosphere of the venue. \n  \nOn behalf of the Organizing Committee of the 13th European Federation of Electron Paramagnetic Resonance (EFEPR) Conference and the accompanying Young Researcher Conference (yEFEPR)\, I am pleased to invite you to join us in Brno\, Czech Republic\, from 29 August to 5 September 2026\, at the OREA Congress Hotel.\nThe yEFEPR conference\, dedicated to young scientists in magnetic resonance\, will take place during the first two days and will be followed by the main EFEPR 2026 conference. \nThis year’s EFEPR holds special significance: it takes place on the 100th anniversary of Josef Dadok (28 February 1926 – 4 October 2024)\, a renowned Czech scientist\, and magnetic resonance pioneer – a name deeply intertwined with the history of EPR and NMR in Czechoslovakia. \nDadok graduated from Brno University of Technology in the early 50s. In 1960\, he founded the Nuclear Magnetic Resonance Department at the Institute of Scientific Instruments (ISI)\, Czechoslovak Academy of Sciences\, where he\, together with his team\, developed the first devices for NMR spectroscopy in Czechoslovakia. At that time\, an embargo from the US on NMR equipment to the Soviet Bloc made scientific progress difficult. Luckily\, ISI was just ten minutes from TESLA Brno – the state-sponsored monopoly on electronics production in Czechoslovakia. In 1965\, TESLA put Dadok’s first 60 MHz spectrometer\, the TESLA BS477\, into production\, making Czechoslovakia the third country\, after the USA and Japan\, to succeed in the serial production of these scientific devices. This was the only production of its kind in the Eastern Bloc\, which continued for 25 years\, resulting in about 500 TESLA spectrometers. \nIn 1967\, Professor Dadok left for an internship in the USA and did not return after the Soviet occupation of Czechoslovakia in 1968. In 1976\, he became Technical Director of the Pittsburgh National NMR Centre and full professor at Carnegie Mellon University. A year later\, he developed the first 600 MHz superconducting spectrometer (14.1 T)\, which remained the most powerful high-resolution NMR system in the world for eight years. \nDadok’s legacy remains alive in Brno. Since 2013\, the National NMR Centre at CEITEC has carried his name and houses the most powerful spectrometer in Central and Eastern Europe. Moreover\, my team at the Magneto-Optical and THz Spectroscopy group aims to reestablish the tradition of magnetic resonance development in Brno\, started by Josef Dadok. You can read more about the history of EPR in Czechoslovakia and Dadok’s legacy in our recent paper. \nI am honored to host EFEPR 2026 in a city so deeply tied to Josef Dadok’s legacy. I believe his spirit of scientific excellence will inspire all participants. \nOn behalf of the Organizing Committee\, I warmly invite you to register and join us for what promises to be an exciting and memorable meeting. \nWe look forward to welcoming you to Brno in 2026! \nWarm regards\,\nOn behalf of the Organizing Committee\nPetr Neugebauer
URL:https://czechsemiconductorcentre.cz/event/european-federation-of-electron-paramagnetic-resonance-efepr/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/09/Snimek-obrazovky-2025-09-18-143926.png
ORGANIZER;CN="CEITEC BUT":MAILTO:Marcela.Frybortova@ceitec.vutbr.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260823
DTEND;VALUE=DATE:20260829
DTSTAMP:20260923T100010
CREATED:20260223T083900Z
LAST-MODIFIED:20260223T083900Z
UID:2064-1787443200-1787961599@czechsemiconductorcentre.cz
SUMMARY:ECS Summer School 2026 - Application deadline 29 March
DESCRIPTION:WHEN: August 23th – August 28th\, 2026 \nWHERE: University Residential Centre\, University of Bologna\, Bertinoro\, Italy \nThe program will cover four main topics: \n\nSemiconductor technology\nIntegrated Circuits design\nDigital systems and Embedded Intelligence\nIntegration\n\nTalks will be delivered by representatives from leading universities\, research institutes and companies. Career testimonies by young engineers will complete the week. \nEligibility criteria: This Summer School is dedicated to undergraduate students who\, by the time of the summer school\, will have completed at least two years of university study and will have at least one year to go before completing their undergraduate studies. Students from all fields of STEM (Science\, Technology\, Engineering and Mathematics) in a university based in the EU or associated country are eligible to apply. A good knowledge of English is mandatory since all interaction will be held in that language. \nSelection will be based on the applicant’s CV\, a motivation letter\, up to three recommendation letters\, and academic transcripts. It will take into account gender and geographical balance to ensure a diversity of student backgrounds. \nCost: Free of charge. Accommodation and meals are provided. Please note that travel costs are not reimbursed. \nApplication deadline: 29 March 2026. \nREGISTRATION HERE.
URL:https://czechsemiconductorcentre.cz/event/ecs-summer-school-2026-application-deadline-29-march/
LOCATION:University of Bologna\, Via Frangipane 6\, Bertinoro\, Italy
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/02/Snimek-obrazovky-2026-02-23-093839.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260821
DTEND;VALUE=DATE:20260823
DTSTAMP:20260923T100010
CREATED:20260720T063814Z
LAST-MODIFIED:20260720T063814Z
UID:2572-1787270400-1787443199@czechsemiconductorcentre.cz
SUMMARY:Chips Venture Forum Selection at INPHO Venture Summit
DESCRIPTION:Semiconductor start-ups are invited to apply for the Chips Venture Forum Selection\, taking place in Bordeaux on 21–22 October 2026. The event will connect promising European innovators with investors\, corporate partners\, semiconductor end-users and representatives of key European institutions. \nThe opportunity is open to semiconductor-related start-ups that are established or legally registered in a country hosting an operational Competence Centre within the European network\, as well as to beneficiaries of the European Innovation Council. \nWhy apply?\nSelected start-ups will have the opportunity to: \n\npresent their technologies and business propositions to leading venture capital funds and corporate partners;\ntake part in qualified meetings with investors and potential industrial partners;\nincrease their visibility within the European semiconductor ecosystem;\nengage with representatives of the Chips Competence Centres\, Pilot Lines\, the European Design Platform\, the European Innovation Council and the European Commission;\nexplore investment\, commercialisation and scaling opportunities.\n\nThe Chips Venture Forum is organised by Blumorpho within the aCCCess project\, in collaboration with DG CONNECT and the European Innovation Council. Its objective is to accelerate the development\, financing and industrial adoption of semiconductor technologies while strengthening Europe’s semiconductor ecosystem. \nContinue the conversation at the INPHO Venture Summit\nSelected companies will also have the opportunity to participate in the INPHO Venture Summit on 22–23 October 2026 at the Palais de la Bourse in Bordeaux. \nThe invitation-only summit brings together deep-tech investors\, venture capital funds\, large corporations and selected start-ups. It offers participating companies a valuable opportunity to continue discussions with investors while meeting semiconductor end-users and other key industry stakeholders. \nChips Venture Forum Selection\n21–22 October 2026\nBordeaux\, France \nINPHO Venture Summit\n22–23 October 2026\nPalais de la Bourse\, Bordeaux\, France \nLearn more and apply through the Chips Venture Forum website \nDiscover the INPHO Venture Summit
URL:https://czechsemiconductorcentre.cz/event/chips-venture-forum-selection-at-inpho-venture-summit/
LOCATION:Bordeaux\, Bordeaux \, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/07/x-1.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260817
DTEND;VALUE=DATE:20260822
DTSTAMP:20260923T100010
CREATED:20260507T064136Z
LAST-MODIFIED:20260507T064136Z
UID:2258-1786924800-1787356799@czechsemiconductorcentre.cz
SUMMARY:CEITEC Student Talent Summer School 2026
DESCRIPTION:Applying for CEITEC Student Talent Summer School 2026\n\nThe summer school is aimed at high school students in the third grade\, but any high school student can apply.\nAs we are limited by the size of the labs and the number of students/mentor\, participants are selected based on cover letters that they supply as part of the application process.\nWe consider the reasons why the student would like to attend the Summer School\, why they chose the topic\, how participation could help them in their future studies\, etc. Cover letters are evaluated directly by the mentors of the research projects.\nApplications are open until 30 June 2026.\n\n  \nInterested in applying?\n\nChoose the topic that you want to pursue – you should always apply for a specific research project.\nApply by email to Marcela.Frybortova@ceitec.vutbr.cz – the email must state your chosen research project as well as a short cover letter in which you outline why you chose the topic\, what made you interested in it\, and why it could benefit you personally.\nPut “Summer School 2026” in the subject line.\nApply by 30 June 2026\, when the application period closes.\nIf you are selected\, we will contact you at the very end of June with instructions on how to make your registration binding via our website. The binding registration will entail paying a registration fee of 500 CZK.\nWe will provide food and board for participants throughout the duration of the programme at a nearby dormitory (7-minute walk).\n\n  \nProgramme:\nDay 1 (Monday\, August 17\, 2026)\n\n 8:00 – 9:00 | Participant Registration\n 9:00 – 10:00 | Official Opening\n10:00 – 11:00 | Orientation Walk Around the CEITEC BUT Campus\n11:00 – 13:00 | Check-in at the Dormitory\n13:00 – 17:00 | Lab Work\n17:00 – 18:00 | Meeting with an Alumnus\n18:00 – 21:00 | BBQ and Improvised Networking (CEITEC BUT Courtyard)\n\n  \nDay 2 (Tuesday\, August 18\, 2026)\n\n 9:00 – 13:00 | Lab Work\n14:00 – 17:00 | Programme in Brno City Centre\n17:00 – 18:00 | Hands-On Science with Stanislav Průša\, Summer School Expert Guarantor\n18:00 – 20:00 | Pub Quiz\n\n  \nDay 3 (Wednesday\, August 19\, 2026)\n\n 9:00 – 13:00 | Lab Work\n14:00 – 16:00 | Field Trip to Thermo Fisher Scientific\n17:00 – 19:00 | Lab Work\n19:00 – 21:00 | Movie Night\n\n  \nDay 4 (Thursday\, August 20\, 2026)\n\n9:00 – 12:00 | Laboratory Program (Group Rotation and Opportunity to Try a Different Research Project)\n13:00 – 15:00 | Expert Lecture\n15:00 – 19:00 | Project Presentation Preparation\n\n  \nDay 5 (Friday\, August 21\, 2026)\n\n9:00 – 12:00 | Project Presentations and Official Closing
URL:https://czechsemiconductorcentre.cz/event/ceitec-student-talent-summer-school-2026/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1777463370180.jpg
ORGANIZER;CN="CEITEC BUT":MAILTO:Marcela.Frybortova@ceitec.vutbr.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260707T100000
DTEND;TZID=Europe/Prague:20260707T113000
DTSTAMP:20260923T100010
CREATED:20260617T082750Z
LAST-MODIFIED:20260617T082750Z
UID:2472-1783418400-1783423800@czechsemiconductorcentre.cz
SUMMARY:aCCCess Webinar Series on Technology Offers - FAMES PL & ASTEERICS CCC
DESCRIPTION:Join us on July 7 at 10:00 CEST for the third webinar of the aCCCess series dedicated to European Pilot Lines and their collaboration with Competence Centers. \nIn this session\, discover how the FAMES Pilot Line\, the euroCDP and the ASTEERICS Chips Competence Center support innovation from chip design to silicon validation and industrialisation. Through concrete feedback from Soitec and Nellow\, explore how Europe’s semiconductor ecosystem helps de-risk innovation and accelerate market readiness.. \n 📍 Programme : \n 10:00 – 10:05   Introduction: European Chips Act context\, aCCCess project. \nAn Innovation Continuum: From Upstream to Downstream \nLaure de Tassigny – European Projects Manager- Minalogic \n10:05 – 10:12   FAMES Pilot Line: Presentation of FAMES sub-10nm technologies and Open Access \nSusana Bonnetier – Open Access Chairperson – European FAMES Pilot Line – CEA \n 10:12 – 10:15   EuroCDP: Design resources and support services \nOlivier Thomas – Deputy head of the Integrated Circuit & System division – DET IC Dash – CEA \n 10:15 – 10:22 – Industrial Testimonial: How FAMES helps de-risk silicon innovation? (sSOI\, cybersecurity) \nSébastien Lasserre – FDSOI Product Manager – Soitec \n 10:22 – 10:32   ASTEERICS: Chips Competence Center mission\, free training offer and ASIC support services \nPhilippe Flatresse – Director of Valorisation\, ASTEERICS Chips Competence Center \n 10:32 – 10:40   Start-up Testimonial: FESO technology integration\, support and fundraising journey \nJean Philippe Attané – CEO – Nellow \n10:40 – 11:00   Q&A \n\n\nWe strongly encourage you to register here and to disseminate this event in your networks using the attached visuals (this webinar is public and open to your end-users).\n\n  \n About aCCCess webinar series on Technology offers \nEach session spotlights one pilot line and one competence centre and also focus on collaborations between ENCCC actors and user experiences. \nThese sessions will help our communities to understand \n• What are pilot lines and how can their services be accessed?\n• What technological resources in microelectronics exist in European ecosystems and how can they be leveraged?\n• Do European Competence Centres offer services complementary to each other? \n 
URL:https://czechsemiconductorcentre.cz/event/acccess-webinar-series-on-technology-offers-fames-pl-asteerics-ccc/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Webinar-Technology3_1200x1200.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260629T130000
DTEND;TZID=Europe/Prague:20260629T143000
DTSTAMP:20260923T100010
CREATED:20260529T092510Z
LAST-MODIFIED:20260529T092657Z
UID:2417-1782738000-1782743400@czechsemiconductorcentre.cz
SUMMARY:Building the Future Together: Integrating Sustainability in the Semiconductor Ecosystem
DESCRIPTION:This joint webinar by GENESIS and the European Chips Skills Academy (ECSA) explores how sustainability and workforce development can shape the semiconductor industry’s future. The session will highlight the role of PFAS in semiconductor manufacturing\, the challenges\, and how the GENESIS project is working with industry partners to identify safer and more sustainable alternatives. Participants will also gain insight into how ECSA is helping equip the next generation of semiconductor professionals with the skills needed for a more sustainable ecosystem. \nMore details about the event can be found here. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/building-the-future-together-integrating-sustainability-in-the-semiconductor-ecosystem/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/June-1.png.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260624T093000
DTEND;TZID=Europe/Prague:20260624T150000
DTSTAMP:20260923T100010
CREATED:20260616T070136Z
LAST-MODIFIED:20260616T070136Z
UID:2469-1782293400-1782313200@czechsemiconductorcentre.cz
SUMMARY:Digital Europe Program Online National Information Day
DESCRIPTION:Funding for AI\, cybersecurity\, advanced digital skills\, and European data infrastructure for 2026 is now open\, and we’ll show you how to get involved—all in one place. \nCzechInvest and the Ministry of Industry and Trade invite you to the Digital Europe Program Online National Information Day\, which will take place on Wednesday\, June 24\, 2026\, starting at 9:30 a.m. online via the MS Teams platform. \nThe Digital Europe program provides businesses\, research organizations\, and public administration with access to cutting-edge digital technologies and European funding. At the info day\, you will learn: \n\nwhich calls are currently open and what is expected of applicants\,\nwhat the funding rules\, eligibility criteria\, and most common mistakes in applications are\,\nhow to link Digital Europe with synergies from the Horizon Europe program\,\nand how the European network of national contact points DEP4ALL can help you with your preparation.\n\nSpeakers will include Kristina Kardum\, Head of the Digital Europe Program Sector at the European Commission (her presentation will be in English)\, along with experts from CzechInvest\, NÚKIB\, and the Prague Technology Center. \nThe event is intended for companies\, research organizations\, and public administration bodies considering submitting an application to the Digital Europe program: whether you have a specific project proposal or are just considering whether the program is right for you. The current calls for proposals close in early October. Since the summer significantly shortens the effective time for preparation\, it pays to start looking for partners and building a consortium right now\, as a high-quality international project cannot be put together in just a few weeks. \nA follow-up opportunity to find project partners: immediately after the info day\, on the same day from 1:00 PM to 3:00 PM\, the DEP Online Matchmaking Event (in English) will take place\, focused on partnerships for the current (10th) call of the Digital Europe Program. You can look forward to a presentation of partner search tools (the b2match platform)\, thematic breakout sessions on the calls\, short participant pitches\, and networking. \nParticipation is free after registration. Please register for both events HERE: we will send you the access link to MS Teams via email before the event. The program is subject to minor changes.
URL:https://czechsemiconductorcentre.cz/event/digital-europe-program-online-national-information-day/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Logo_Digitalni_Evropa.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260624
DTEND;VALUE=DATE:20260625
DTSTAMP:20260923T100010
CREATED:20260402T073253Z
LAST-MODIFIED:20260402T073253Z
UID:2180-1782259200-1782345599@czechsemiconductorcentre.cz
SUMMARY:Analog IC Design Using Open Source Tools and IHP-Open-PDK
DESCRIPTION:Date: June 24\, 2026 \nTime: 8:30 – 18:30 \nLocation: Poznan University of Technology \nParticipant limit: 15 people (first come\, first served) \nParticipation fee: 100 EUR (the price does not include VAT\, students are exempt from the fee). Registration is on a first-come\, first-served basis. \nWorkshop format: Interactive demonstration with the possibility to work at stations prepared by the organizer. Personal computers are not required; however\, participants may use their own laptops if they wish. \nAgenda:\n\n8:30 – 9:00 – Participant registration\, organizational introduction\n9:00 – 10:30 – Introduction to analog design in an open-source environment (overview of tools: Xschem\, Ngspice\, IHP-Open-PDK\, workflow basics)\n10:30 – 10:45 – Coffee break\n10:45 – 12:30 – Analog schematic design in Xschem – best practices\, parameterization\, DC\, AC\, and transient simulations (live demonstration)\n12:30 – 13:30 – Lunch break\n13:30 – 15:00 – Design of a sample analog circuit (e.g.\, StrongARM latch comparator) – operation analysis\, Monte Carlo simulations\, mismatch analysis\, parameter verification\n15:00 – 15:15 – Coffee break\n15:15 – 17:00 – Introduction to layout in KLayout\, analog design principles (matching\, symmetry\, noise minimization)\, PyCells – mask design automation\n17:00 – 18:00 – Complete design flow: from schematic to verification (LVS/DRC – process overview)\, fillers\, chip finishing\, sign-off\n18:00 – 18:30 – Q&A session\, workshop summary\n\nTechnical Scope\n\nFundamentals of CMOS analog circuit design\nWorking with open-source tools in a design environment\nElectrical simulations and interpretation of results\nIntroduction to analog layout and good design practices\nOverview of the complete design flow (schematic → simulation → layout → verification)\n\n 
URL:https://czechsemiconductorcentre.cz/event/analog-ic-design-using-open-source-tools-and-ihp-open-pdk/
LOCATION:Poznan\, Poznan\, Poland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/2024-UMEL-Laborky-12-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260618T140000
DTEND;TZID=Europe/Prague:20260618T170000
DTSTAMP:20260923T100010
CREATED:20260529T093358Z
LAST-MODIFIED:20260529T093430Z
UID:2421-1781791200-1781802000@czechsemiconductorcentre.cz
SUMMARY:Info Session on the Chips 2026 Calls on Skills
DESCRIPTION:Responding to the growing semiconductor skills shortage in Europe and the objectives of the European Chips Act\, the Chips Joint Undertaking is launching three dedicated Skills-related Calls in July 2026 to support ambitious initiatives in semiconductor education\, training\, re-skilling\, up-skilling and talent development across the European ecosystem. \nTo help the community better understand these upcoming opportunities and prepare future collaborations\, the Chips JU Office\, in cooperation with AENEAS\, EPoSS and INSIDE is organising the Info Session on the Chips JU 2026 Calls on Skills. \nAgenda \n14:00 – 14:05 Welcome & Opening \n\nMatei Arghirescu\, Chips JU Office\nCaroline Bedran / Patrick Cogez\, AENEAS\n\nIntroduction to the Skills Calls context and Europe’s semiconductor talent challenge. \n14:05 – 15:00     Block 1: Skills Hubs of Excellence (HoE): Moderated by Patrick Cogez\, AENEAS \n\nPresentation of the Call by the Chips JU Office\nEuropean Commission perspective (Stefano Selleri\, DG CONNECT)\nNational representatives (TBD)\nCommunity project idea presentation(s)\nQ&A session\n\n15:00 – 15:05 Short Break \n15:05 – 16:00     Block 2: Pilot Federation \nSame structure- European Commission perspective (Stefano Selleri\, DG CONNECT) \n16:00 – 16:05 Short Break \n16:05 – 17:00      Block 3: Stimulation of Chip Design \nSame structure- European Commission perspective (Marco Ceccarelli\, DG CONNECT) \n17:00 – 17:05 Closing Remarks\nRegistration is free of charge and available here.
URL:https://czechsemiconductorcentre.cz/event/info-session-on-the-chips-2026-calls-on-skills/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1779806475660.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260616
DTEND;VALUE=DATE:20260620
DTSTAMP:20260923T100010
CREATED:20260313T110551Z
LAST-MODIFIED:20260313T110749Z
UID:2110-1781568000-1781913599@czechsemiconductorcentre.cz
SUMMARY:EPoSS Annual Forum 2026
DESCRIPTION:The EPoSS Annual Forum 2026 will take place from June 16-19 in Braga\, Portugal\, kindly hosted by the EPoSS member INL. \nThe Annual Forum offers sessions with high-ranking representatives from the EU\, local authorities\, institutions and companies\, thematic sessions\, poster presentations\, start-up award pitch and award ceremony\, on-site visits to thematically relevant institutions as well as time for exchange and idea development. \nBringing together key stakeholders from across Europe\, the forum will offer a rich and dynamic programme\, including: \n\nSessions with high-ranking representatives from the European Union\, local authorities\, research institutions\, and industry;\nThematic sessions addressing strategic and emerging topics in smart systems integration;\nPoster presentations showcasing cutting-edge research and innovation;\nA start-up award pitch session\, followed by the award ceremony.\n\nThe event will provide a unique platform to connect policy\, research\, and industry within one of Portugal’s leading innovation hubs\, fostering dialogue and collaboration around the future of smart systems integration.
URL:https://czechsemiconductorcentre.cz/event/eposs-annual-forum-2026/
LOCATION:INL – International Iberian Nanotechnology Laboratory\, Av. Mte. José Veiga s/n\, Braga\, 4715-330\, Portugal
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/EPOSS2026_General-scaled-1.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260615
DTEND;VALUE=DATE:20260618
DTSTAMP:20260923T100010
CREATED:20260602T070546Z
LAST-MODIFIED:20260604T101214Z
UID:2431-1781481600-1781740799@czechsemiconductorcentre.cz
SUMMARY:20th Silicon Saxony Days
DESCRIPTION:The Czech Semiconductor Centre will be part of this year’s Silicon Saxony Days\, one of Europe’s key high-tech and semiconductor networking events\, bringing together industry\, research\, start-ups and policy leaders from across the European ecosystem. We are pleased to highlight the participation of Petr Kamenický\, the new Director of Czech Semiconductor Centre\, with his talk: Accelerating Semiconductor Innovation in Europe: AI\, Energy and Open Architectures. His contribution on June 16 will underline the Czech Semiconductor Centre’s role in strengthening Czechia’s position within the European semiconductor landscape and supporting closer cooperation across European innovation ecosystems. This talk presents how the Czech semiconductor ecosystem – through the CSC and Czech National Semiconductor Cluster – accelerates innovation in AI hardware\, energy-efficient semiconductors and open architectures such as RISC-V\, strengthening Europe’s semiconductor value chain. \nThe programme will also feature Jana Drbohlavová\, Deputy Director of the Czech Semiconductor Centre\, who will join the panel discussion: Common challenges\, common goals: European Semiconductor Initiatives on Monday\, June 15 with Pierre Chastanet from European Commission. \n \nWe look forward to connecting with partners\, innovators and decision-makers in Dresden and contributing to the discussion on how Europe can accelerate semiconductor innovation through collaboration\, open architectures\, AI and energy-aware technologies. See you at Silicon Saxony Days 2026. \nMore details here.
URL:https://czechsemiconductorcentre.cz/event/20th-silicon-saxony-days/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Snimek-obrazovky-2026-06-02-090521.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260610T110000
DTEND;TZID=Europe/Prague:20260610T120000
DTSTAMP:20260923T100010
CREATED:20260604T095321Z
LAST-MODIFIED:20260604T095321Z
UID:2453-1781089200-1781092800@czechsemiconductorcentre.cz
SUMMARY:ALL2GaN Insights: Driving Greener Power Electronics
DESCRIPTION:We are pleased to invite you to the next session of the ALL2GaN Insights: Driving Greener Power Electronics – The Wednesday Webinar Series. \nWebinar #5: QuanFINE high-performance substrates for power applications and devicesDate: Wednesday\, 10 June 2026Time: 11:00 a.m.Format: Live online via WebExDuration: 60 minutesParticipation: Public event with open registration \nThe webinar will focus on QuanFINE high-performance substrates for power applications and devices and will feature two speakers closely involved in the ALL2GaN project: \nMichael Salter\, RISE Research Institute of SwedenAnders Lundskog\, SweGaN \nMichael Salter will present the latest results of RISE GaN HEMT device development within the ALL2GaN project\, including E-mode/D-mode devices using SweGaN QuanFINE GaN/SiC epi substrates and vertical nanowire HEMT devices. \nAnders Lundskog will introduce SweGaN and QuanFINE Epitaxy\, followed by an overview of Mg-doping profile tuning. \nThe webinar offers an opportunity to discover recent developments in GaN technology\, learn from European research and industry experts\, and engage with the speakers during a live Q&A session. \nJoin the webinar:https://infineon.webex.com/infineon/j.php?MTID=m86ed1962316e3106cf041e32852b7f2f
URL:https://czechsemiconductorcentre.cz/event/all2gan-insights-driving-greener-power-electronics/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/shutterstock_2550090433-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260609T100000
DTEND;TZID=Europe/Prague:20260609T110000
DTSTAMP:20260923T100010
CREATED:20260604T094550Z
LAST-MODIFIED:20260604T094550Z
UID:2449-1780999200-1781002800@czechsemiconductorcentre.cz
SUMMARY:Technology Offers & Collaboration Pathways with NanoIC Pilot Line and FC3 Chips Competence Center
DESCRIPTION:Join us on June 9 for the second webinar of the aCCCess series dedicated to European Pilot Lines. \nThis session will feature the NanoIC Pilot Line and the FC3 Chips Competence Center\, showcasing cutting-edge capabilities and illustrating how their partnership enables seamless access to expertise\, services\, and innovation support. Don’t miss this opportunity to explore how these synergies accelerate the path from research to industrial application across Europe. It is free of charge. Please register here. \n📍 Programme : \n\n10:00 – 10:05 Introduction – aCCCess project\n\nLaure de Tassigny – European Project Manager\, Minalogic \n\n10:05 – 10:15 NanoIC Introduction and Access model\n\nGiuseppe Fiorentino – Programme Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:15 – 10:25NanoIC Technology offer\n\nNina Bazzazian R&D Project Leader – NanoIC Pilot Line Outreach and Access\, IMEC \n\n10:25 – 10:35 NanoIC Workforce and Training opportunities\n\nRuxandra Marina Florea – R&D Project Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:35 – 10:50 FC3 Chips Competence Center approach to tailored trainings\n\nDavid Maes Research Valorization Manager\, FC3 Chips Competence Center – KU Leuven \n\n10:50 – 11:00 Q&A
URL:https://czechsemiconductorcentre.cz/event/technology-offers-collaboration-pathways-with-nanoic-pilot-line-and-fc3-chips-competence-center/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/1778664216731.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260609
DTEND;VALUE=DATE:20260610
DTSTAMP:20260923T100010
CREATED:20260529T122352Z
LAST-MODIFIED:20260529T123149Z
UID:2425-1780963200-1781049599@czechsemiconductorcentre.cz
SUMMARY:Q-LAB Grand Opening
DESCRIPTION:We are pleased to invite you to the official opening of Q-LAB\, a state-of-the-art technical cleanliness laboratory developed by QPAG in cooperation with ZEISS\, taking place on 9 June 2026 at the QPAG Technology Centre in Brno. \nIn today’s manufacturing environment\, even microscopic contaminants can significantly affect product performance\, durability and safety. Q-LAB has been established as a specialised centre for technical cleanliness testing and contamination analysis in accordance with VDA 19.1 / ISO 16232 standards\, operating in an ISO 7 cleanroom environment. \nWhat to Expect\n\nExpert presentations on technical cleanliness and quality assurance\nParticle analysis demonstrations in cooperation with ZEISS\nGuided tours of the QPAG Technology Centre\nLive demonstrations of:\n\nQ-LAB technical cleanliness laboratory (ISO 7)\nAccredited calibration laboratory\nPrecision measurement and 3D scanning technologies\nAutomated quality control solutions\nAI-powered visual inspection systems\n\n\nNetworking opportunities with industry professionals and technology partners\n\nEvent Details\n📅 Date: 9 June 2026📍 Venue: QPAG Technology Centre\, Kaštanová 530/125b\, Brno\, Czech Republic🕘 Morning Session: Registration 08:30 | Opening 09:00 (full)🕐 Afternoon Session: Registration 12:30 | Opening 13:00(Both sessions feature the same programme content.) \nThe event is intended for manufacturing and technical directors\, quality management professionals\, process engineers and specialists from the automotive\, aerospace\, engineering\, medical and high-tech industries. \nFor registration and further information\, please visit:Q-LAB Registration & Event Details \nWe look forward to welcoming you to Q-LAB and sharing the future of technical cleanliness\, advanced inspection and quality assurance. ✨
URL:https://czechsemiconductorcentre.cz/event/q-lab-grand-opening/
LOCATION:Lab Q-LAB\, Kaštanová 125b\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/ttt-scaled-uai-1032x688-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260608
DTEND;VALUE=DATE:20260613
DTSTAMP:20260923T100010
CREATED:20260324T125511Z
LAST-MODIFIED:20260324T125721Z
UID:2162-1780876800-1781308799@czechsemiconductorcentre.cz
SUMMARY:RISC-V Summit Europe
DESCRIPTION:Join us at the RISC-V Summit Europe 2026\, the leading European event dedicated to the open standard RISC-V architecture and its rapidly evolving ecosystem. \nTaking place in Bologna\, Italy\, from 8–12 June 2026\, the summit brings together key stakeholders from industry\, academia\, research\, and government to explore the future of computing and innovation built on RISC-V. \nThe programme will feature: \n\nInspiring keynotes and technical sessions\nPanels\, tutorials\, and workshops\nIndustry exhibitions\, demos\, and poster sessions\nExtensive networking opportunities with leaders across semiconductors\, AI\, embedded systems\, HPC\, and beyond\n\nRISC-V\, as an open and flexible instruction set architecture\, is enabling new applications and research that are shaping the future of computing in Europe and globally. \nThe summit offers a unique platform to exchange knowledge\, showcase innovations\, and strengthen collaboration across the European and global RISC-V community. \n📍 Location: Bologna Congress Center\, Italy📅 Dates: 8–12 June 2026🔗 Learn more and register: RISC-V Summit Europe 2026 website
URL:https://czechsemiconductorcentre.cz/event/risc-v-summit-europe-2/
LOCATION:Bologna\, Bologna\, Italy
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-24-135153.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260606
DTSTAMP:20260923T100010
CREATED:20260521T081219Z
LAST-MODIFIED:20260521T081247Z
UID:2373-1780531200-1780703999@czechsemiconductorcentre.cz
SUMMARY:European Semiconductor Collaborations Days
DESCRIPTION:Chips Without Borders will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. \nHungarian SMEs\, industrial stakeholders\, and the HCHiP consortium itself will present their profiles\, ideas\, and international collaboration opportunities. This event also provides an opportunity for CCCs and our other European partners to present themselves\, their profiles\, and the areas in which they are seeking partners through posters and presentations. \nMore informations: https://hchip.hu/en/2026/04/15/european-semiconductor-collaboration-days-2/ \nEuropean Semiconductor Collaboration Day\, taking place on 4–5 June 2026 in Budapest\, Hungary. “Chips Without Borders” will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. Venue: Novotel Budapest Danube (Budapest\, Bem rakpart 33-34\, 1027) The participation is free\, but it requires registration. \nRegister here: https://lnkd.in/dB2mS2kG \nFor questions\, please contact us at: hchip@hchip.hu
URL:https://czechsemiconductorcentre.cz/event/european-semiconductor-collaborations-days/
LOCATION:Budapest\, Budapest\, Hungary
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778062652574-Hchip_European_Semiconductor_Collaboration_Days_cover.webp
ORGANIZER;CN="Hchip":MAILTO:hchip@hchip.hu
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260605
DTSTAMP:20260923T100010
CREATED:20260520T091830Z
LAST-MODIFIED:20260520T091902Z
UID:2361-1780531200-1780617599@czechsemiconductorcentre.cz
SUMMARY:Forming\, storming\, norming and performing of European Semiconductor startups meetup
DESCRIPTION:EuroCDP and Silicon Catalyst.EU (via Malta Semiconductor Competence Centre) are co‑hosting the EU Semiconductor FSNP Meetup – targeted working day bringing together semiconductor startups\, VCs\, corporates\, and ecosystem leaders. \nWelcome to forming\, storming\, norming and performing of European semiconductor startups. This is a curated afternoon and evening event\, focusing exclusively on semiconductor startups and investors. The beautiful chateau location has been carefully chosen for easy access from Bordeaux station and airport for your same day arrival from anywhere in Europe. You will enjoy high-value conversations without the noise of broader tech events as the sun sets over the vineyards of the most hallowed wine growing soil in the world. \n​We have a packed agenda of investor insights\, funding discussions\, fast-paced startup pitch sessions and a deep insight into the geopolitical semiconductor dynamics challenging Europe’s chip ecosystem. \nDesigned for founders\, VCs\, and ecosystem leaders\, the day aims to spark meaningful connections and knowledge sharing. \nThe day closes by enjoying the finest wines in the world at our Bordeaux wine tasting social event led by one of the region’s top female sommeliers. \n​The event is free and dedicated to startup founders\, investors and ecosystem leaders. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/forming-storming-norming-and-performing-of-european-semiconductor-startups-meetup/
LOCATION:Château de Seguin\, 3 Chem. du Bon Coin\, Lignan-de-Bordeaux\, 33360\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778664931554.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260603
DTEND;VALUE=DATE:20260604
DTSTAMP:20260923T100010
CREATED:20260408T074732Z
LAST-MODIFIED:20260408T074732Z
UID:2188-1780444800-1780531199@czechsemiconductorcentre.cz
SUMMARY:SEMI Europe Policy Forum 2026
DESCRIPTION:Join leading policymakers\, industry executives and technology experts at the SEMI Europe Policy Forum 2026\, a high-level gathering dedicated to shaping the future of Europe’s semiconductor ecosystem. \nIn an era defined by rapid geopolitical shifts and technological transformation\, Europe faces both unprecedented challenges and unique opportunities. This year’s forum will explore how Europe can strengthen its strategic position\, enhance supply chain resilience\, and secure long-term economic competitiveness in the global semiconductor landscape. \n\nWhy Attend?\nThe SEMI Europe Policy Forum brings together key stakeholders from across the semiconductor value chain and public sector to: \n\nExamine the impact of global geopolitical dynamics on Europe’s technology leadership\nDiscuss the next phase of the European Chips Act and its role in securing Europe’s tech future\nAddress sustainability and competitiveness challenges across the industry\nExplore strategies for building a skilled workforce for the future\nFoster international collaboration and strategic partnerships\n\n\nWho Should Attend?\nThis forum is designed for decision-makers and influencers\, including: \n\nEU and national policymakers\, public sector leaders and diplomatic representatives\nSenior executives and industry leaders from semiconductor and technology companies\nR&D professionals\, innovation leaders and supply chain stakeholders\nRepresentatives from academia\, research institutions and think tanks\n\n\nProgramme Highlights\nParticipants can look forward to a full-day programme featuring: \n\nHigh-level keynote sessions and panel discussions\nExpert insights on policy\, innovation and competitiveness\nNetworking opportunities with European and global leaders\nEvening reception and networking dinner\n\nKey topics include Europe’s tech sovereignty\, workforce development\, sustainability challenges\, and global partnerships shaping the future of semiconductors. \n\nBe Part of the Conversation\nAs Europe navigates a rapidly evolving global landscape\, collaboration between industry and policymakers has never been more critical. The SEMI Europe Policy Forum offers a unique platform to exchange ideas\, influence policy direction\, and contribute to a resilient and competitive European semiconductor ecosystem. \n👉 Register now
URL:https://czechsemiconductorcentre.cz/event/semi-europe-policy-forum-2026/
LOCATION:Brussels\, Brussels\, Belgium
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/04/SEPF_360x317px.png.webp
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BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260522T130000
DTEND;TZID=Europe/Prague:20260522T170000
DTSTAMP:20260923T100010
CREATED:20260520T092202Z
LAST-MODIFIED:20260520T092309Z
UID:2367-1779454800-1779469200@czechsemiconductorcentre.cz
SUMMARY:NanoIC Webinar
DESCRIPTION:Join this online webinar to discover the NanoIC Pilot Line and its cutting-edge technologies for next-generation semiconductor innovation. The session will include an introduction to the pilot line\, presentations on advanced logic\, novel embedded memories\, and advanced interconnect technologies\, as well as information on how to access the pilot line and upcoming training and workforce development opportunities. \nPreliminary Agenda \n\nNanoIC Pilot Line: Introduction\nGiuseppe Fiorentino\nNanoIC Technologies\n\nAdvanced Logic – Yasser Sherazi\nNovel Embedded Memories – Marie Garcia Bardon\nAdvanced Interconnect – Nicolas Pantano\n\n\nAccess to the Pilot Line\nNina Bazzazian\nTraining and Workforce Development\nRuxandra Marina Florea\n\nRead more about NanoIC: https://www.nanoic-project.eu/en \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/nanoic-webinar/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778582712459.jpg
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260521
DTEND;VALUE=DATE:20260522
DTSTAMP:20260923T100010
CREATED:20260504T074829Z
LAST-MODIFIED:20260525T075119Z
UID:2252-1779321600-1779407999@czechsemiconductorcentre.cz
SUMMARY:Verification Academy Live Brno
DESCRIPTION:Verification Academy Live Brno brings together engineers and researchers from industry and academia to examine advances in functional verification. The program covers the Questa One toolchain\, AI-assisted verification workflows\, and stimulus-free approaches that combine static and formal analysis to uncover issues earlier and more efficiently. \nDYNANIC is co-organizing this event and contributing three sessions to the program  including a technical presentation\, a research-grounded overview\, and a panel discussion. \n\n\n\n\n\n\n\n\nThe seminar also addresses how verification IP continues to evolve to address increasing design complexity\, improve coverage quality\, and reduce overall project risk. Topics directly relevant to FPGA-based system development. \nGet more information & registration here: https://dyna-nic.com/dynanic-at-verification-academy-live/ 
URL:https://czechsemiconductorcentre.cz/event/where-verification-methodology-meets-real-world-practice/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/DYNANIC-preview-general.webp
ORGANIZER;CN="DynaNIC":MAILTO:info@dyna-nic.com
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260521
DTEND;VALUE=DATE:20260522
DTSTAMP:20260923T100010
CREATED:20260320T091517Z
LAST-MODIFIED:20260320T091517Z
UID:2152-1779321600-1779407999@czechsemiconductorcentre.cz
SUMMARY:PIXEurope Connect
DESCRIPTION:Join PIXEurope Connect – Industry Ecosystem Building Day\, taking place on 21 May 2026 in Barcelona. \nOrganized within the framework of the PIXEurope Pilot Line – coordinated by ICFO and co-funded by the Chips Joint Undertaking and participating Member States\, with support from regional authorities – this event will be the first to bring together end-users\, technology providers\, industry leaders and policymakers around this Pan-European initiative. \nThe event will highlight the value of the PIXEurope infrastructure and its role in strengthening Europe’s integrated photonics ecosystem. Through presentations and collaborative sessions\, participants will explore how the Pilot Line can accelerate the adoption of integrated photonic chips\, reinforcing Europe’s technological sovereignty and fostering new industrial and scientific opportunities. \nThe venue of the event will be Torre Glòries\, one of Barcelona’s most iconic landmarks. Located at the entrance to the 22@ innovation district – an ideal setting for PIXEurope’s mission to bridge the gap between research and industrial readiness in advanced photonic integrated circuits.
URL:https://czechsemiconductorcentre.cz/event/pixeurope-connect/
LOCATION:Barcelona\, Barcelona\, Spain
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-20-101451.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260923T100010
CREATED:20260311T113719Z
LAST-MODIFIED:20260520T092505Z
UID:2102-1779062400-1779321599@czechsemiconductorcentre.cz
SUMMARY:Czech Semicon Days 2026
DESCRIPTION:Join us at Czech Semicon Days 2026\, one of the key events for the semiconductor sector in Central Europe. \nFrom 18–20 May 2026 in Prague\, industry leaders\, researchers\, investors and policymakers will come together to discuss the future of semiconductors and their role in next-generation mobility\, autonomous systems and electrification. \nThe programme will feature expert discussions\, networking opportunities and specialised events connecting companies across the semiconductor value chain and strengthening the Czech and European semiconductor ecosystem. \nWe are also pleased to highlight that the Czech Semiconductor Centre will be presenting at the event\, showcasing its role in the European network of competence centres and its activities supporting research\, innovation and collaboration between industry and academia in chip technologies. \nThe programme of Czech Semicon Days 2026 will begin on 18–19 May in Prague\, bringing together industry leaders\, policymakers\, investors and researchers to discuss the future of semiconductors and their role in next-generation mobility. The first day at Bohemia Pavilion\, Výstaviště Prague will feature specialised ecosystem events such as Supplier Day\, focused on strengthening connections across the semiconductor supply chain\, followed by the Czech Semiconductor Ecosystem Development Day\, dedicated to advancing the national semiconductor ecosystem and improving regional readiness to attract new industry investments. On 19 May\, the main conference Czech Investment Forum: Semiconductors for Future Mobility will take place in the historic Fantova Building at Prague’s main railway station\, with keynote speeches\, expert presentations and panel discussions on industry–academia collaboration\, semiconductor innovation hubs and resilient European semiconductor ecosystems. \nThe programme will then continue on 20 May in Brno at the Advanced Chip Design Research Center (ACDRC)\, where participants will gain direct insight into advanced research and collaboration opportunities in semiconductor design and innovation. This will be followed by additional accompanying events and networking activities throughout the week\, providing further opportunities for industry partners\, researchers and policymakers to deepen collaboration\, explore investment opportunities and strengthen the Czech Republic’s role within the European semiconductor value chain. \nCzech Semicon Days provide a unique opportunity to:\n• meet key stakeholders in the European semiconductor ecosystem\n• explore collaboration opportunities across industry and research\n• discuss investment and technology trends shaping the future of semiconductors \n📍 Prague\, Czech Republic\n📅 18–20 May 2026 \nMore information: https://czechsemicondays.com/
URL:https://czechsemiconductorcentre.cz/event/czech-semicon-days-2026/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/ChatGPT-Image-11.-3.-2026-12_46_34.png
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BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260513T110000
DTEND;TZID=Europe/Prague:20260513T170000
DTSTAMP:20260923T100010
CREATED:20260507T075412Z
LAST-MODIFIED:20260507T075412Z
UID:2263-1778670000-1778691600@czechsemiconductorcentre.cz
SUMMARY:Invitation to the Webinar#4 ALL2GaN Insights: Driving Greener Power Electronics
DESCRIPTION:ALL2GaN Insights: Driving Greener Power Electronics – The Wednesday Webinar Series \nWebinar#4 : 13.05.2026 at 11 a.m. \nNovelties in HV GaN power devices from ALL2GaN \nPresenters: Gianmauro POZZOVIVO (Infineon Technologies Austria AG)\, Elison MATIOLI (EPFL)\, Iordan DOYTCHINOV (Corintis) \nThe webinar hosts three participants who cooperate very strictly in the ALL2GaN project. \nStarting with Gianmauro\, he will present the development and industrialization of 650 V GaN-on-Si power technology on 200 mm wafers\, covering advances in epitaxy\, device processes\, and manufacturing readiness. It highlights the enablement of large-scale production of normally-off lateral GaN HEMTs\, the qualification of lead products for industrial market release\, and briefly outlines future directions toward integrated GaN solutions. \n\n\n\nJoin from the meeting link\n\n\nhttps://infineon.webex.com/infineon/j.php?MTID=m812b4bc8d4194bbbba4041d1eaa50219\n\n\n\n\n\n\n\nJoin by meeting number\n\n\nMeeting number (access code): 2780 340 0314\n\n\nMeeting password: X3gZ5pgGgq2\n\n\n\nAbout the Speakers : \n\n\n\n\n\nName / Surname\nGianmauro POZZOVIVO\nElison MATIOLI\nIordan DOYTCHINOV\n\n\nOrganisation / University\nInfineon Technologies Austria AG\nEPFL\nCorintis SA\n\n\nTitle in the Organisation\nDirector\nProfessor and Director of the POWERlab\nSenior Program Manager\n\n\nRole in ALL2GaN Project\nIn the All2GaN project\, I contribute to WP2 by developing and industrializing best‑in‑class 650V lateral GaN technology (advanced epitaxy and device processing) and advancing integrated high‑voltage GaN solutions through monolithic power ICs and system‑in‑package approaches\, targeting production readiness and market release.\nPartner in Task 2\, O2.3: Breaking the limits: Realizing most advanced GaN HEMT device and integration concepts\nSenior Program Manager responsible for leading Corintis contribution on demonstrating value of topology optimized cooling for future high power (data center applications) GaN modules.\n\n\nAcademic Background\nPhD in Electrotechnics from TU Vienna (2010)\, focused on optimizing GaN HEMTs. Joined Infineon Austria in 2010 as an early GaN technology development engineer\, working on FEOL development plus wafer- and package-level characterization. From 2015–2020\, I managed the development of the first-generation normally-off high-voltage GaN power devices\, launched as CoolGaN in 2021. Today\, I lead High Voltage GaN Technology Development\, managing a team of 20 engineers.\nGaN power devices\nPhD in Precision Engineering (Cranfield University)\, EPFL; background as Principle Investigator on AI research related to drone GPS free navigation systems\, Corintis related scientific contributions in the area of co-packaged and designed cooling.\n\n\nWhat excites you about the project?\nALL2GaN excites me because it’s about speeding up real GaN adoption\, giving engineers practical tools and support to integrate GaN across major applications faster and at scale. That’s the kind of push that can make GaN the next mainstream power semiconductor\nTo develop technologies that can reveal the true capabilities of GaN\nThe opportunity to enable higher-efficiency power electronics for future data centers by integrating advanced microfluidic cooling directly into next-generation GaN power modules.\n\n\nWhat is the biggest challenge in making power electronics greener? [nbsp]\nThe biggest challenge is getting GaN into real products at scale\, making sure it’s reliable in the field\, cost-competitive\, and the supply chain can actually support volume. That’s when “greener” savings become real.\nTo make full use of the GaN properties\nManaging rising heat flux while ensuring efficiency\, reliability\, and scalable manufacturing.\n\n\nLinkedIn\nhttps://www.linkedin.com/in/gianmauro-pozzovivo-66a99a26/ \nhttps://www.linkedin.com/in/elison-matioli-74ab1586/  \nhttps://www.linkedin.com/in/iordan-doytchinov-21b18045/
URL:https://czechsemiconductorcentre.cz/event/invitation-to-the-webinar4-all2gan-insights-driving-greener-power-electronics/
LOCATION:on-line
CATEGORIES:External Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260505
DTEND;VALUE=DATE:20260507
DTSTAMP:20260923T100010
CREATED:20260311T112857Z
LAST-MODIFIED:20260311T112933Z
UID:2098-1777939200-1778111999@czechsemiconductorcentre.cz
SUMMARY:Power Semiconductor Devices & Technologies | ECPE Tutorial | ONLINE
DESCRIPTION:The tutorial is aimed at engineers who are engaged in power electronics and want to improve their knowledge and understanding of power devices including the developments expected in near future. \nThe course starts with a general overview on required power device properties and a very basic treatment of semiconductor material and device physics. Blocking capability of the devices\, unipolar and bipolar current transport and gate control will be discussed. Diodes\, MOS transistors (including compensated superjunction MOS) and Insulated Gate Bipolar Transistors (IGBT) will be treated in detail including their dynamical properties\, safe operation and temperature limits. The wide bandgap semiconductor materials silicon carbide and gallium nitride have become important competitors to silicon. Their superior properties for application and the expectations for the next years will be discussed. Also\, issues concerning control\, packaging and integration will be treated in the corresponding contributions. The following chapters demonstrate basic principles of power electronic systems and the basics of intelligent IGBT / MOSFET control circuits. MOS transistor and IGBT gate drivers for various fields of application are discussed in detail. Finally a short overview of hybrid power electronic integration and the most relevant aspects (cooling\, reliability and EMC problems) will be presented. \n  \n\n\n\n\n\n\n\nDate: 05/05/2026 – 06/05/2026 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nLocation: Digital Event \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Chair: \nDr. Anton Mauder\, Infineon Technologies (DE)\nProf. Nando Kaminski\, University of Bremen (DE) \n\nECPE Contact:\nMarietta Di Dio\n+49 911 81 02 88 – 13\nmarietta.didio@ecpe.org \n\nRegistration Deadline: 28 April 2026
URL:https://czechsemiconductorcentre.cz/event/power-semiconductor-devices-technologies-ecpe-tutorial-online/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-11-122756.png
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
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