BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Czech Semiconductor Centre - ECPv6.15.18//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Czech Semiconductor Centre
X-ORIGINAL-URL:https://czechsemiconductorcentre.cz
X-WR-CALDESC:Events for Czech Semiconductor Centre
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/Prague
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20260329T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20261025T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20270328T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20271031T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260821
DTEND;VALUE=DATE:20260823
DTSTAMP:20260923T184910
CREATED:20260720T063814Z
LAST-MODIFIED:20260720T063814Z
UID:2572-1787270400-1787443199@czechsemiconductorcentre.cz
SUMMARY:Chips Venture Forum Selection at INPHO Venture Summit
DESCRIPTION:Semiconductor start-ups are invited to apply for the Chips Venture Forum Selection\, taking place in Bordeaux on 21–22 October 2026. The event will connect promising European innovators with investors\, corporate partners\, semiconductor end-users and representatives of key European institutions. \nThe opportunity is open to semiconductor-related start-ups that are established or legally registered in a country hosting an operational Competence Centre within the European network\, as well as to beneficiaries of the European Innovation Council. \nWhy apply?\nSelected start-ups will have the opportunity to: \n\npresent their technologies and business propositions to leading venture capital funds and corporate partners;\ntake part in qualified meetings with investors and potential industrial partners;\nincrease their visibility within the European semiconductor ecosystem;\nengage with representatives of the Chips Competence Centres\, Pilot Lines\, the European Design Platform\, the European Innovation Council and the European Commission;\nexplore investment\, commercialisation and scaling opportunities.\n\nThe Chips Venture Forum is organised by Blumorpho within the aCCCess project\, in collaboration with DG CONNECT and the European Innovation Council. Its objective is to accelerate the development\, financing and industrial adoption of semiconductor technologies while strengthening Europe’s semiconductor ecosystem. \nContinue the conversation at the INPHO Venture Summit\nSelected companies will also have the opportunity to participate in the INPHO Venture Summit on 22–23 October 2026 at the Palais de la Bourse in Bordeaux. \nThe invitation-only summit brings together deep-tech investors\, venture capital funds\, large corporations and selected start-ups. It offers participating companies a valuable opportunity to continue discussions with investors while meeting semiconductor end-users and other key industry stakeholders. \nChips Venture Forum Selection\n21–22 October 2026\nBordeaux\, France \nINPHO Venture Summit\n22–23 October 2026\nPalais de la Bourse\, Bordeaux\, France \nLearn more and apply through the Chips Venture Forum website \nDiscover the INPHO Venture Summit
URL:https://czechsemiconductorcentre.cz/event/chips-venture-forum-selection-at-inpho-venture-summit/
LOCATION:Bordeaux\, Bordeaux \, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/07/x-1.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260817
DTEND;VALUE=DATE:20260822
DTSTAMP:20260923T184910
CREATED:20260507T064136Z
LAST-MODIFIED:20260507T064136Z
UID:2258-1786924800-1787356799@czechsemiconductorcentre.cz
SUMMARY:CEITEC Student Talent Summer School 2026
DESCRIPTION:Applying for CEITEC Student Talent Summer School 2026\n\nThe summer school is aimed at high school students in the third grade\, but any high school student can apply.\nAs we are limited by the size of the labs and the number of students/mentor\, participants are selected based on cover letters that they supply as part of the application process.\nWe consider the reasons why the student would like to attend the Summer School\, why they chose the topic\, how participation could help them in their future studies\, etc. Cover letters are evaluated directly by the mentors of the research projects.\nApplications are open until 30 June 2026.\n\n  \nInterested in applying?\n\nChoose the topic that you want to pursue – you should always apply for a specific research project.\nApply by email to Marcela.Frybortova@ceitec.vutbr.cz – the email must state your chosen research project as well as a short cover letter in which you outline why you chose the topic\, what made you interested in it\, and why it could benefit you personally.\nPut “Summer School 2026” in the subject line.\nApply by 30 June 2026\, when the application period closes.\nIf you are selected\, we will contact you at the very end of June with instructions on how to make your registration binding via our website. The binding registration will entail paying a registration fee of 500 CZK.\nWe will provide food and board for participants throughout the duration of the programme at a nearby dormitory (7-minute walk).\n\n  \nProgramme:\nDay 1 (Monday\, August 17\, 2026)\n\n 8:00 – 9:00 | Participant Registration\n 9:00 – 10:00 | Official Opening\n10:00 – 11:00 | Orientation Walk Around the CEITEC BUT Campus\n11:00 – 13:00 | Check-in at the Dormitory\n13:00 – 17:00 | Lab Work\n17:00 – 18:00 | Meeting with an Alumnus\n18:00 – 21:00 | BBQ and Improvised Networking (CEITEC BUT Courtyard)\n\n  \nDay 2 (Tuesday\, August 18\, 2026)\n\n 9:00 – 13:00 | Lab Work\n14:00 – 17:00 | Programme in Brno City Centre\n17:00 – 18:00 | Hands-On Science with Stanislav Průša\, Summer School Expert Guarantor\n18:00 – 20:00 | Pub Quiz\n\n  \nDay 3 (Wednesday\, August 19\, 2026)\n\n 9:00 – 13:00 | Lab Work\n14:00 – 16:00 | Field Trip to Thermo Fisher Scientific\n17:00 – 19:00 | Lab Work\n19:00 – 21:00 | Movie Night\n\n  \nDay 4 (Thursday\, August 20\, 2026)\n\n9:00 – 12:00 | Laboratory Program (Group Rotation and Opportunity to Try a Different Research Project)\n13:00 – 15:00 | Expert Lecture\n15:00 – 19:00 | Project Presentation Preparation\n\n  \nDay 5 (Friday\, August 21\, 2026)\n\n9:00 – 12:00 | Project Presentations and Official Closing
URL:https://czechsemiconductorcentre.cz/event/ceitec-student-talent-summer-school-2026/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1777463370180.jpg
ORGANIZER;CN="CEITEC BUT":MAILTO:Marcela.Frybortova@ceitec.vutbr.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260707T100000
DTEND;TZID=Europe/Prague:20260707T113000
DTSTAMP:20260923T184910
CREATED:20260617T082750Z
LAST-MODIFIED:20260617T082750Z
UID:2472-1783418400-1783423800@czechsemiconductorcentre.cz
SUMMARY:aCCCess Webinar Series on Technology Offers - FAMES PL & ASTEERICS CCC
DESCRIPTION:Join us on July 7 at 10:00 CEST for the third webinar of the aCCCess series dedicated to European Pilot Lines and their collaboration with Competence Centers. \nIn this session\, discover how the FAMES Pilot Line\, the euroCDP and the ASTEERICS Chips Competence Center support innovation from chip design to silicon validation and industrialisation. Through concrete feedback from Soitec and Nellow\, explore how Europe’s semiconductor ecosystem helps de-risk innovation and accelerate market readiness.. \n 📍 Programme : \n 10:00 – 10:05   Introduction: European Chips Act context\, aCCCess project. \nAn Innovation Continuum: From Upstream to Downstream \nLaure de Tassigny – European Projects Manager- Minalogic \n10:05 – 10:12   FAMES Pilot Line: Presentation of FAMES sub-10nm technologies and Open Access \nSusana Bonnetier – Open Access Chairperson – European FAMES Pilot Line – CEA \n 10:12 – 10:15   EuroCDP: Design resources and support services \nOlivier Thomas – Deputy head of the Integrated Circuit & System division – DET IC Dash – CEA \n 10:15 – 10:22 – Industrial Testimonial: How FAMES helps de-risk silicon innovation? (sSOI\, cybersecurity) \nSébastien Lasserre – FDSOI Product Manager – Soitec \n 10:22 – 10:32   ASTEERICS: Chips Competence Center mission\, free training offer and ASIC support services \nPhilippe Flatresse – Director of Valorisation\, ASTEERICS Chips Competence Center \n 10:32 – 10:40   Start-up Testimonial: FESO technology integration\, support and fundraising journey \nJean Philippe Attané – CEO – Nellow \n10:40 – 11:00   Q&A \n\n\nWe strongly encourage you to register here and to disseminate this event in your networks using the attached visuals (this webinar is public and open to your end-users).\n\n  \n About aCCCess webinar series on Technology offers \nEach session spotlights one pilot line and one competence centre and also focus on collaborations between ENCCC actors and user experiences. \nThese sessions will help our communities to understand \n• What are pilot lines and how can their services be accessed?\n• What technological resources in microelectronics exist in European ecosystems and how can they be leveraged?\n• Do European Competence Centres offer services complementary to each other? \n 
URL:https://czechsemiconductorcentre.cz/event/acccess-webinar-series-on-technology-offers-fames-pl-asteerics-ccc/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Webinar-Technology3_1200x1200.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260629T130000
DTEND;TZID=Europe/Prague:20260629T143000
DTSTAMP:20260923T184910
CREATED:20260529T092510Z
LAST-MODIFIED:20260529T092657Z
UID:2417-1782738000-1782743400@czechsemiconductorcentre.cz
SUMMARY:Building the Future Together: Integrating Sustainability in the Semiconductor Ecosystem
DESCRIPTION:This joint webinar by GENESIS and the European Chips Skills Academy (ECSA) explores how sustainability and workforce development can shape the semiconductor industry’s future. The session will highlight the role of PFAS in semiconductor manufacturing\, the challenges\, and how the GENESIS project is working with industry partners to identify safer and more sustainable alternatives. Participants will also gain insight into how ECSA is helping equip the next generation of semiconductor professionals with the skills needed for a more sustainable ecosystem. \nMore details about the event can be found here. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/building-the-future-together-integrating-sustainability-in-the-semiconductor-ecosystem/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/June-1.png.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260624T093000
DTEND;TZID=Europe/Prague:20260624T150000
DTSTAMP:20260923T184910
CREATED:20260616T070136Z
LAST-MODIFIED:20260616T070136Z
UID:2469-1782293400-1782313200@czechsemiconductorcentre.cz
SUMMARY:Digital Europe Program Online National Information Day
DESCRIPTION:Funding for AI\, cybersecurity\, advanced digital skills\, and European data infrastructure for 2026 is now open\, and we’ll show you how to get involved—all in one place. \nCzechInvest and the Ministry of Industry and Trade invite you to the Digital Europe Program Online National Information Day\, which will take place on Wednesday\, June 24\, 2026\, starting at 9:30 a.m. online via the MS Teams platform. \nThe Digital Europe program provides businesses\, research organizations\, and public administration with access to cutting-edge digital technologies and European funding. At the info day\, you will learn: \n\nwhich calls are currently open and what is expected of applicants\,\nwhat the funding rules\, eligibility criteria\, and most common mistakes in applications are\,\nhow to link Digital Europe with synergies from the Horizon Europe program\,\nand how the European network of national contact points DEP4ALL can help you with your preparation.\n\nSpeakers will include Kristina Kardum\, Head of the Digital Europe Program Sector at the European Commission (her presentation will be in English)\, along with experts from CzechInvest\, NÚKIB\, and the Prague Technology Center. \nThe event is intended for companies\, research organizations\, and public administration bodies considering submitting an application to the Digital Europe program: whether you have a specific project proposal or are just considering whether the program is right for you. The current calls for proposals close in early October. Since the summer significantly shortens the effective time for preparation\, it pays to start looking for partners and building a consortium right now\, as a high-quality international project cannot be put together in just a few weeks. \nA follow-up opportunity to find project partners: immediately after the info day\, on the same day from 1:00 PM to 3:00 PM\, the DEP Online Matchmaking Event (in English) will take place\, focused on partnerships for the current (10th) call of the Digital Europe Program. You can look forward to a presentation of partner search tools (the b2match platform)\, thematic breakout sessions on the calls\, short participant pitches\, and networking. \nParticipation is free after registration. Please register for both events HERE: we will send you the access link to MS Teams via email before the event. The program is subject to minor changes.
URL:https://czechsemiconductorcentre.cz/event/digital-europe-program-online-national-information-day/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Logo_Digitalni_Evropa.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260624
DTEND;VALUE=DATE:20260625
DTSTAMP:20260923T184910
CREATED:20260402T073253Z
LAST-MODIFIED:20260402T073253Z
UID:2180-1782259200-1782345599@czechsemiconductorcentre.cz
SUMMARY:Analog IC Design Using Open Source Tools and IHP-Open-PDK
DESCRIPTION:Date: June 24\, 2026 \nTime: 8:30 – 18:30 \nLocation: Poznan University of Technology \nParticipant limit: 15 people (first come\, first served) \nParticipation fee: 100 EUR (the price does not include VAT\, students are exempt from the fee). Registration is on a first-come\, first-served basis. \nWorkshop format: Interactive demonstration with the possibility to work at stations prepared by the organizer. Personal computers are not required; however\, participants may use their own laptops if they wish. \nAgenda:\n\n8:30 – 9:00 – Participant registration\, organizational introduction\n9:00 – 10:30 – Introduction to analog design in an open-source environment (overview of tools: Xschem\, Ngspice\, IHP-Open-PDK\, workflow basics)\n10:30 – 10:45 – Coffee break\n10:45 – 12:30 – Analog schematic design in Xschem – best practices\, parameterization\, DC\, AC\, and transient simulations (live demonstration)\n12:30 – 13:30 – Lunch break\n13:30 – 15:00 – Design of a sample analog circuit (e.g.\, StrongARM latch comparator) – operation analysis\, Monte Carlo simulations\, mismatch analysis\, parameter verification\n15:00 – 15:15 – Coffee break\n15:15 – 17:00 – Introduction to layout in KLayout\, analog design principles (matching\, symmetry\, noise minimization)\, PyCells – mask design automation\n17:00 – 18:00 – Complete design flow: from schematic to verification (LVS/DRC – process overview)\, fillers\, chip finishing\, sign-off\n18:00 – 18:30 – Q&A session\, workshop summary\n\nTechnical Scope\n\nFundamentals of CMOS analog circuit design\nWorking with open-source tools in a design environment\nElectrical simulations and interpretation of results\nIntroduction to analog layout and good design practices\nOverview of the complete design flow (schematic → simulation → layout → verification)\n\n 
URL:https://czechsemiconductorcentre.cz/event/analog-ic-design-using-open-source-tools-and-ihp-open-pdk/
LOCATION:Poznan\, Poznan\, Poland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/2024-UMEL-Laborky-12-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260618T140000
DTEND;TZID=Europe/Prague:20260618T170000
DTSTAMP:20260923T184910
CREATED:20260529T093358Z
LAST-MODIFIED:20260529T093430Z
UID:2421-1781791200-1781802000@czechsemiconductorcentre.cz
SUMMARY:Info Session on the Chips 2026 Calls on Skills
DESCRIPTION:Responding to the growing semiconductor skills shortage in Europe and the objectives of the European Chips Act\, the Chips Joint Undertaking is launching three dedicated Skills-related Calls in July 2026 to support ambitious initiatives in semiconductor education\, training\, re-skilling\, up-skilling and talent development across the European ecosystem. \nTo help the community better understand these upcoming opportunities and prepare future collaborations\, the Chips JU Office\, in cooperation with AENEAS\, EPoSS and INSIDE is organising the Info Session on the Chips JU 2026 Calls on Skills. \nAgenda \n14:00 – 14:05 Welcome & Opening \n\nMatei Arghirescu\, Chips JU Office\nCaroline Bedran / Patrick Cogez\, AENEAS\n\nIntroduction to the Skills Calls context and Europe’s semiconductor talent challenge. \n14:05 – 15:00     Block 1: Skills Hubs of Excellence (HoE): Moderated by Patrick Cogez\, AENEAS \n\nPresentation of the Call by the Chips JU Office\nEuropean Commission perspective (Stefano Selleri\, DG CONNECT)\nNational representatives (TBD)\nCommunity project idea presentation(s)\nQ&A session\n\n15:00 – 15:05 Short Break \n15:05 – 16:00     Block 2: Pilot Federation \nSame structure- European Commission perspective (Stefano Selleri\, DG CONNECT) \n16:00 – 16:05 Short Break \n16:05 – 17:00      Block 3: Stimulation of Chip Design \nSame structure- European Commission perspective (Marco Ceccarelli\, DG CONNECT) \n17:00 – 17:05 Closing Remarks\nRegistration is free of charge and available here.
URL:https://czechsemiconductorcentre.cz/event/info-session-on-the-chips-2026-calls-on-skills/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1779806475660.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260616
DTEND;VALUE=DATE:20260620
DTSTAMP:20260923T184910
CREATED:20260313T110551Z
LAST-MODIFIED:20260313T110749Z
UID:2110-1781568000-1781913599@czechsemiconductorcentre.cz
SUMMARY:EPoSS Annual Forum 2026
DESCRIPTION:The EPoSS Annual Forum 2026 will take place from June 16-19 in Braga\, Portugal\, kindly hosted by the EPoSS member INL. \nThe Annual Forum offers sessions with high-ranking representatives from the EU\, local authorities\, institutions and companies\, thematic sessions\, poster presentations\, start-up award pitch and award ceremony\, on-site visits to thematically relevant institutions as well as time for exchange and idea development. \nBringing together key stakeholders from across Europe\, the forum will offer a rich and dynamic programme\, including: \n\nSessions with high-ranking representatives from the European Union\, local authorities\, research institutions\, and industry;\nThematic sessions addressing strategic and emerging topics in smart systems integration;\nPoster presentations showcasing cutting-edge research and innovation;\nA start-up award pitch session\, followed by the award ceremony.\n\nThe event will provide a unique platform to connect policy\, research\, and industry within one of Portugal’s leading innovation hubs\, fostering dialogue and collaboration around the future of smart systems integration.
URL:https://czechsemiconductorcentre.cz/event/eposs-annual-forum-2026/
LOCATION:INL – International Iberian Nanotechnology Laboratory\, Av. Mte. José Veiga s/n\, Braga\, 4715-330\, Portugal
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/EPOSS2026_General-scaled-1.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260615
DTEND;VALUE=DATE:20260618
DTSTAMP:20260923T184910
CREATED:20260602T070546Z
LAST-MODIFIED:20260604T101214Z
UID:2431-1781481600-1781740799@czechsemiconductorcentre.cz
SUMMARY:20th Silicon Saxony Days
DESCRIPTION:The Czech Semiconductor Centre will be part of this year’s Silicon Saxony Days\, one of Europe’s key high-tech and semiconductor networking events\, bringing together industry\, research\, start-ups and policy leaders from across the European ecosystem. We are pleased to highlight the participation of Petr Kamenický\, the new Director of Czech Semiconductor Centre\, with his talk: Accelerating Semiconductor Innovation in Europe: AI\, Energy and Open Architectures. His contribution on June 16 will underline the Czech Semiconductor Centre’s role in strengthening Czechia’s position within the European semiconductor landscape and supporting closer cooperation across European innovation ecosystems. This talk presents how the Czech semiconductor ecosystem – through the CSC and Czech National Semiconductor Cluster – accelerates innovation in AI hardware\, energy-efficient semiconductors and open architectures such as RISC-V\, strengthening Europe’s semiconductor value chain. \nThe programme will also feature Jana Drbohlavová\, Deputy Director of the Czech Semiconductor Centre\, who will join the panel discussion: Common challenges\, common goals: European Semiconductor Initiatives on Monday\, June 15 with Pierre Chastanet from European Commission. \n \nWe look forward to connecting with partners\, innovators and decision-makers in Dresden and contributing to the discussion on how Europe can accelerate semiconductor innovation through collaboration\, open architectures\, AI and energy-aware technologies. See you at Silicon Saxony Days 2026. \nMore details here.
URL:https://czechsemiconductorcentre.cz/event/20th-silicon-saxony-days/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Snimek-obrazovky-2026-06-02-090521.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260610T110000
DTEND;TZID=Europe/Prague:20260610T120000
DTSTAMP:20260923T184910
CREATED:20260604T095321Z
LAST-MODIFIED:20260604T095321Z
UID:2453-1781089200-1781092800@czechsemiconductorcentre.cz
SUMMARY:ALL2GaN Insights: Driving Greener Power Electronics
DESCRIPTION:We are pleased to invite you to the next session of the ALL2GaN Insights: Driving Greener Power Electronics – The Wednesday Webinar Series. \nWebinar #5: QuanFINE high-performance substrates for power applications and devicesDate: Wednesday\, 10 June 2026Time: 11:00 a.m.Format: Live online via WebExDuration: 60 minutesParticipation: Public event with open registration \nThe webinar will focus on QuanFINE high-performance substrates for power applications and devices and will feature two speakers closely involved in the ALL2GaN project: \nMichael Salter\, RISE Research Institute of SwedenAnders Lundskog\, SweGaN \nMichael Salter will present the latest results of RISE GaN HEMT device development within the ALL2GaN project\, including E-mode/D-mode devices using SweGaN QuanFINE GaN/SiC epi substrates and vertical nanowire HEMT devices. \nAnders Lundskog will introduce SweGaN and QuanFINE Epitaxy\, followed by an overview of Mg-doping profile tuning. \nThe webinar offers an opportunity to discover recent developments in GaN technology\, learn from European research and industry experts\, and engage with the speakers during a live Q&A session. \nJoin the webinar:https://infineon.webex.com/infineon/j.php?MTID=m86ed1962316e3106cf041e32852b7f2f
URL:https://czechsemiconductorcentre.cz/event/all2gan-insights-driving-greener-power-electronics/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/shutterstock_2550090433-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260609T100000
DTEND;TZID=Europe/Prague:20260609T110000
DTSTAMP:20260923T184910
CREATED:20260604T094550Z
LAST-MODIFIED:20260604T094550Z
UID:2449-1780999200-1781002800@czechsemiconductorcentre.cz
SUMMARY:Technology Offers & Collaboration Pathways with NanoIC Pilot Line and FC3 Chips Competence Center
DESCRIPTION:Join us on June 9 for the second webinar of the aCCCess series dedicated to European Pilot Lines. \nThis session will feature the NanoIC Pilot Line and the FC3 Chips Competence Center\, showcasing cutting-edge capabilities and illustrating how their partnership enables seamless access to expertise\, services\, and innovation support. Don’t miss this opportunity to explore how these synergies accelerate the path from research to industrial application across Europe. It is free of charge. Please register here. \n📍 Programme : \n\n10:00 – 10:05 Introduction – aCCCess project\n\nLaure de Tassigny – European Project Manager\, Minalogic \n\n10:05 – 10:15 NanoIC Introduction and Access model\n\nGiuseppe Fiorentino – Programme Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:15 – 10:25NanoIC Technology offer\n\nNina Bazzazian R&D Project Leader – NanoIC Pilot Line Outreach and Access\, IMEC \n\n10:25 – 10:35 NanoIC Workforce and Training opportunities\n\nRuxandra Marina Florea – R&D Project Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:35 – 10:50 FC3 Chips Competence Center approach to tailored trainings\n\nDavid Maes Research Valorization Manager\, FC3 Chips Competence Center – KU Leuven \n\n10:50 – 11:00 Q&A
URL:https://czechsemiconductorcentre.cz/event/technology-offers-collaboration-pathways-with-nanoic-pilot-line-and-fc3-chips-competence-center/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/1778664216731.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260609
DTEND;VALUE=DATE:20260610
DTSTAMP:20260923T184910
CREATED:20260529T122352Z
LAST-MODIFIED:20260529T123149Z
UID:2425-1780963200-1781049599@czechsemiconductorcentre.cz
SUMMARY:Q-LAB Grand Opening
DESCRIPTION:We are pleased to invite you to the official opening of Q-LAB\, a state-of-the-art technical cleanliness laboratory developed by QPAG in cooperation with ZEISS\, taking place on 9 June 2026 at the QPAG Technology Centre in Brno. \nIn today’s manufacturing environment\, even microscopic contaminants can significantly affect product performance\, durability and safety. Q-LAB has been established as a specialised centre for technical cleanliness testing and contamination analysis in accordance with VDA 19.1 / ISO 16232 standards\, operating in an ISO 7 cleanroom environment. \nWhat to Expect\n\nExpert presentations on technical cleanliness and quality assurance\nParticle analysis demonstrations in cooperation with ZEISS\nGuided tours of the QPAG Technology Centre\nLive demonstrations of:\n\nQ-LAB technical cleanliness laboratory (ISO 7)\nAccredited calibration laboratory\nPrecision measurement and 3D scanning technologies\nAutomated quality control solutions\nAI-powered visual inspection systems\n\n\nNetworking opportunities with industry professionals and technology partners\n\nEvent Details\n📅 Date: 9 June 2026📍 Venue: QPAG Technology Centre\, Kaštanová 530/125b\, Brno\, Czech Republic🕘 Morning Session: Registration 08:30 | Opening 09:00 (full)🕐 Afternoon Session: Registration 12:30 | Opening 13:00(Both sessions feature the same programme content.) \nThe event is intended for manufacturing and technical directors\, quality management professionals\, process engineers and specialists from the automotive\, aerospace\, engineering\, medical and high-tech industries. \nFor registration and further information\, please visit:Q-LAB Registration & Event Details \nWe look forward to welcoming you to Q-LAB and sharing the future of technical cleanliness\, advanced inspection and quality assurance. ✨
URL:https://czechsemiconductorcentre.cz/event/q-lab-grand-opening/
LOCATION:Lab Q-LAB\, Kaštanová 125b\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/ttt-scaled-uai-1032x688-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260608
DTEND;VALUE=DATE:20260613
DTSTAMP:20260923T184910
CREATED:20260324T125511Z
LAST-MODIFIED:20260324T125721Z
UID:2162-1780876800-1781308799@czechsemiconductorcentre.cz
SUMMARY:RISC-V Summit Europe
DESCRIPTION:Join us at the RISC-V Summit Europe 2026\, the leading European event dedicated to the open standard RISC-V architecture and its rapidly evolving ecosystem. \nTaking place in Bologna\, Italy\, from 8–12 June 2026\, the summit brings together key stakeholders from industry\, academia\, research\, and government to explore the future of computing and innovation built on RISC-V. \nThe programme will feature: \n\nInspiring keynotes and technical sessions\nPanels\, tutorials\, and workshops\nIndustry exhibitions\, demos\, and poster sessions\nExtensive networking opportunities with leaders across semiconductors\, AI\, embedded systems\, HPC\, and beyond\n\nRISC-V\, as an open and flexible instruction set architecture\, is enabling new applications and research that are shaping the future of computing in Europe and globally. \nThe summit offers a unique platform to exchange knowledge\, showcase innovations\, and strengthen collaboration across the European and global RISC-V community. \n📍 Location: Bologna Congress Center\, Italy📅 Dates: 8–12 June 2026🔗 Learn more and register: RISC-V Summit Europe 2026 website
URL:https://czechsemiconductorcentre.cz/event/risc-v-summit-europe-2/
LOCATION:Bologna\, Bologna\, Italy
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-24-135153.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260606
DTSTAMP:20260923T184910
CREATED:20260521T081219Z
LAST-MODIFIED:20260521T081247Z
UID:2373-1780531200-1780703999@czechsemiconductorcentre.cz
SUMMARY:European Semiconductor Collaborations Days
DESCRIPTION:Chips Without Borders will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. \nHungarian SMEs\, industrial stakeholders\, and the HCHiP consortium itself will present their profiles\, ideas\, and international collaboration opportunities. This event also provides an opportunity for CCCs and our other European partners to present themselves\, their profiles\, and the areas in which they are seeking partners through posters and presentations. \nMore informations: https://hchip.hu/en/2026/04/15/european-semiconductor-collaboration-days-2/ \nEuropean Semiconductor Collaboration Day\, taking place on 4–5 June 2026 in Budapest\, Hungary. “Chips Without Borders” will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. Venue: Novotel Budapest Danube (Budapest\, Bem rakpart 33-34\, 1027) The participation is free\, but it requires registration. \nRegister here: https://lnkd.in/dB2mS2kG \nFor questions\, please contact us at: hchip@hchip.hu
URL:https://czechsemiconductorcentre.cz/event/european-semiconductor-collaborations-days/
LOCATION:Budapest\, Budapest\, Hungary
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778062652574-Hchip_European_Semiconductor_Collaboration_Days_cover.webp
ORGANIZER;CN="Hchip":MAILTO:hchip@hchip.hu
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260605
DTSTAMP:20260923T184910
CREATED:20260520T091830Z
LAST-MODIFIED:20260520T091902Z
UID:2361-1780531200-1780617599@czechsemiconductorcentre.cz
SUMMARY:Forming\, storming\, norming and performing of European Semiconductor startups meetup
DESCRIPTION:EuroCDP and Silicon Catalyst.EU (via Malta Semiconductor Competence Centre) are co‑hosting the EU Semiconductor FSNP Meetup – targeted working day bringing together semiconductor startups\, VCs\, corporates\, and ecosystem leaders. \nWelcome to forming\, storming\, norming and performing of European semiconductor startups. This is a curated afternoon and evening event\, focusing exclusively on semiconductor startups and investors. The beautiful chateau location has been carefully chosen for easy access from Bordeaux station and airport for your same day arrival from anywhere in Europe. You will enjoy high-value conversations without the noise of broader tech events as the sun sets over the vineyards of the most hallowed wine growing soil in the world. \n​We have a packed agenda of investor insights\, funding discussions\, fast-paced startup pitch sessions and a deep insight into the geopolitical semiconductor dynamics challenging Europe’s chip ecosystem. \nDesigned for founders\, VCs\, and ecosystem leaders\, the day aims to spark meaningful connections and knowledge sharing. \nThe day closes by enjoying the finest wines in the world at our Bordeaux wine tasting social event led by one of the region’s top female sommeliers. \n​The event is free and dedicated to startup founders\, investors and ecosystem leaders. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/forming-storming-norming-and-performing-of-european-semiconductor-startups-meetup/
LOCATION:Château de Seguin\, 3 Chem. du Bon Coin\, Lignan-de-Bordeaux\, 33360\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778664931554.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260603
DTEND;VALUE=DATE:20260604
DTSTAMP:20260923T184910
CREATED:20260408T074732Z
LAST-MODIFIED:20260408T074732Z
UID:2188-1780444800-1780531199@czechsemiconductorcentre.cz
SUMMARY:SEMI Europe Policy Forum 2026
DESCRIPTION:Join leading policymakers\, industry executives and technology experts at the SEMI Europe Policy Forum 2026\, a high-level gathering dedicated to shaping the future of Europe’s semiconductor ecosystem. \nIn an era defined by rapid geopolitical shifts and technological transformation\, Europe faces both unprecedented challenges and unique opportunities. This year’s forum will explore how Europe can strengthen its strategic position\, enhance supply chain resilience\, and secure long-term economic competitiveness in the global semiconductor landscape. \n\nWhy Attend?\nThe SEMI Europe Policy Forum brings together key stakeholders from across the semiconductor value chain and public sector to: \n\nExamine the impact of global geopolitical dynamics on Europe’s technology leadership\nDiscuss the next phase of the European Chips Act and its role in securing Europe’s tech future\nAddress sustainability and competitiveness challenges across the industry\nExplore strategies for building a skilled workforce for the future\nFoster international collaboration and strategic partnerships\n\n\nWho Should Attend?\nThis forum is designed for decision-makers and influencers\, including: \n\nEU and national policymakers\, public sector leaders and diplomatic representatives\nSenior executives and industry leaders from semiconductor and technology companies\nR&D professionals\, innovation leaders and supply chain stakeholders\nRepresentatives from academia\, research institutions and think tanks\n\n\nProgramme Highlights\nParticipants can look forward to a full-day programme featuring: \n\nHigh-level keynote sessions and panel discussions\nExpert insights on policy\, innovation and competitiveness\nNetworking opportunities with European and global leaders\nEvening reception and networking dinner\n\nKey topics include Europe’s tech sovereignty\, workforce development\, sustainability challenges\, and global partnerships shaping the future of semiconductors. \n\nBe Part of the Conversation\nAs Europe navigates a rapidly evolving global landscape\, collaboration between industry and policymakers has never been more critical. The SEMI Europe Policy Forum offers a unique platform to exchange ideas\, influence policy direction\, and contribute to a resilient and competitive European semiconductor ecosystem. \n👉 Register now
URL:https://czechsemiconductorcentre.cz/event/semi-europe-policy-forum-2026/
LOCATION:Brussels\, Brussels\, Belgium
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/04/SEPF_360x317px.png.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260522T130000
DTEND;TZID=Europe/Prague:20260522T170000
DTSTAMP:20260923T184910
CREATED:20260520T092202Z
LAST-MODIFIED:20260520T092309Z
UID:2367-1779454800-1779469200@czechsemiconductorcentre.cz
SUMMARY:NanoIC Webinar
DESCRIPTION:Join this online webinar to discover the NanoIC Pilot Line and its cutting-edge technologies for next-generation semiconductor innovation. The session will include an introduction to the pilot line\, presentations on advanced logic\, novel embedded memories\, and advanced interconnect technologies\, as well as information on how to access the pilot line and upcoming training and workforce development opportunities. \nPreliminary Agenda \n\nNanoIC Pilot Line: Introduction\nGiuseppe Fiorentino\nNanoIC Technologies\n\nAdvanced Logic – Yasser Sherazi\nNovel Embedded Memories – Marie Garcia Bardon\nAdvanced Interconnect – Nicolas Pantano\n\n\nAccess to the Pilot Line\nNina Bazzazian\nTraining and Workforce Development\nRuxandra Marina Florea\n\nRead more about NanoIC: https://www.nanoic-project.eu/en \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/nanoic-webinar/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778582712459.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260521
DTEND;VALUE=DATE:20260522
DTSTAMP:20260923T184910
CREATED:20260504T074829Z
LAST-MODIFIED:20260525T075119Z
UID:2252-1779321600-1779407999@czechsemiconductorcentre.cz
SUMMARY:Verification Academy Live Brno
DESCRIPTION:Verification Academy Live Brno brings together engineers and researchers from industry and academia to examine advances in functional verification. The program covers the Questa One toolchain\, AI-assisted verification workflows\, and stimulus-free approaches that combine static and formal analysis to uncover issues earlier and more efficiently. \nDYNANIC is co-organizing this event and contributing three sessions to the program  including a technical presentation\, a research-grounded overview\, and a panel discussion. \n\n\n\n\n\n\n\n\nThe seminar also addresses how verification IP continues to evolve to address increasing design complexity\, improve coverage quality\, and reduce overall project risk. Topics directly relevant to FPGA-based system development. \nGet more information & registration here: https://dyna-nic.com/dynanic-at-verification-academy-live/ 
URL:https://czechsemiconductorcentre.cz/event/where-verification-methodology-meets-real-world-practice/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/DYNANIC-preview-general.webp
ORGANIZER;CN="DynaNIC":MAILTO:info@dyna-nic.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260521
DTEND;VALUE=DATE:20260522
DTSTAMP:20260923T184910
CREATED:20260320T091517Z
LAST-MODIFIED:20260320T091517Z
UID:2152-1779321600-1779407999@czechsemiconductorcentre.cz
SUMMARY:PIXEurope Connect
DESCRIPTION:Join PIXEurope Connect – Industry Ecosystem Building Day\, taking place on 21 May 2026 in Barcelona. \nOrganized within the framework of the PIXEurope Pilot Line – coordinated by ICFO and co-funded by the Chips Joint Undertaking and participating Member States\, with support from regional authorities – this event will be the first to bring together end-users\, technology providers\, industry leaders and policymakers around this Pan-European initiative. \nThe event will highlight the value of the PIXEurope infrastructure and its role in strengthening Europe’s integrated photonics ecosystem. Through presentations and collaborative sessions\, participants will explore how the Pilot Line can accelerate the adoption of integrated photonic chips\, reinforcing Europe’s technological sovereignty and fostering new industrial and scientific opportunities. \nThe venue of the event will be Torre Glòries\, one of Barcelona’s most iconic landmarks. Located at the entrance to the 22@ innovation district – an ideal setting for PIXEurope’s mission to bridge the gap between research and industrial readiness in advanced photonic integrated circuits.
URL:https://czechsemiconductorcentre.cz/event/pixeurope-connect/
LOCATION:Barcelona\, Barcelona\, Spain
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-20-101451.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260923T184910
CREATED:20260311T113719Z
LAST-MODIFIED:20260520T092505Z
UID:2102-1779062400-1779321599@czechsemiconductorcentre.cz
SUMMARY:Czech Semicon Days 2026
DESCRIPTION:Join us at Czech Semicon Days 2026\, one of the key events for the semiconductor sector in Central Europe. \nFrom 18–20 May 2026 in Prague\, industry leaders\, researchers\, investors and policymakers will come together to discuss the future of semiconductors and their role in next-generation mobility\, autonomous systems and electrification. \nThe programme will feature expert discussions\, networking opportunities and specialised events connecting companies across the semiconductor value chain and strengthening the Czech and European semiconductor ecosystem. \nWe are also pleased to highlight that the Czech Semiconductor Centre will be presenting at the event\, showcasing its role in the European network of competence centres and its activities supporting research\, innovation and collaboration between industry and academia in chip technologies. \nThe programme of Czech Semicon Days 2026 will begin on 18–19 May in Prague\, bringing together industry leaders\, policymakers\, investors and researchers to discuss the future of semiconductors and their role in next-generation mobility. The first day at Bohemia Pavilion\, Výstaviště Prague will feature specialised ecosystem events such as Supplier Day\, focused on strengthening connections across the semiconductor supply chain\, followed by the Czech Semiconductor Ecosystem Development Day\, dedicated to advancing the national semiconductor ecosystem and improving regional readiness to attract new industry investments. On 19 May\, the main conference Czech Investment Forum: Semiconductors for Future Mobility will take place in the historic Fantova Building at Prague’s main railway station\, with keynote speeches\, expert presentations and panel discussions on industry–academia collaboration\, semiconductor innovation hubs and resilient European semiconductor ecosystems. \nThe programme will then continue on 20 May in Brno at the Advanced Chip Design Research Center (ACDRC)\, where participants will gain direct insight into advanced research and collaboration opportunities in semiconductor design and innovation. This will be followed by additional accompanying events and networking activities throughout the week\, providing further opportunities for industry partners\, researchers and policymakers to deepen collaboration\, explore investment opportunities and strengthen the Czech Republic’s role within the European semiconductor value chain. \nCzech Semicon Days provide a unique opportunity to:\n• meet key stakeholders in the European semiconductor ecosystem\n• explore collaboration opportunities across industry and research\n• discuss investment and technology trends shaping the future of semiconductors \n📍 Prague\, Czech Republic\n📅 18–20 May 2026 \nMore information: https://czechsemicondays.com/
URL:https://czechsemiconductorcentre.cz/event/czech-semicon-days-2026/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/ChatGPT-Image-11.-3.-2026-12_46_34.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260513T110000
DTEND;TZID=Europe/Prague:20260513T170000
DTSTAMP:20260923T184910
CREATED:20260507T075412Z
LAST-MODIFIED:20260507T075412Z
UID:2263-1778670000-1778691600@czechsemiconductorcentre.cz
SUMMARY:Invitation to the Webinar#4 ALL2GaN Insights: Driving Greener Power Electronics
DESCRIPTION:ALL2GaN Insights: Driving Greener Power Electronics – The Wednesday Webinar Series \nWebinar#4 : 13.05.2026 at 11 a.m. \nNovelties in HV GaN power devices from ALL2GaN \nPresenters: Gianmauro POZZOVIVO (Infineon Technologies Austria AG)\, Elison MATIOLI (EPFL)\, Iordan DOYTCHINOV (Corintis) \nThe webinar hosts three participants who cooperate very strictly in the ALL2GaN project. \nStarting with Gianmauro\, he will present the development and industrialization of 650 V GaN-on-Si power technology on 200 mm wafers\, covering advances in epitaxy\, device processes\, and manufacturing readiness. It highlights the enablement of large-scale production of normally-off lateral GaN HEMTs\, the qualification of lead products for industrial market release\, and briefly outlines future directions toward integrated GaN solutions. \n\n\n\nJoin from the meeting link\n\n\nhttps://infineon.webex.com/infineon/j.php?MTID=m812b4bc8d4194bbbba4041d1eaa50219\n\n\n\n\n\n\n\nJoin by meeting number\n\n\nMeeting number (access code): 2780 340 0314\n\n\nMeeting password: X3gZ5pgGgq2\n\n\n\nAbout the Speakers : \n\n\n\n\n\nName / Surname\nGianmauro POZZOVIVO\nElison MATIOLI\nIordan DOYTCHINOV\n\n\nOrganisation / University\nInfineon Technologies Austria AG\nEPFL\nCorintis SA\n\n\nTitle in the Organisation\nDirector\nProfessor and Director of the POWERlab\nSenior Program Manager\n\n\nRole in ALL2GaN Project\nIn the All2GaN project\, I contribute to WP2 by developing and industrializing best‑in‑class 650V lateral GaN technology (advanced epitaxy and device processing) and advancing integrated high‑voltage GaN solutions through monolithic power ICs and system‑in‑package approaches\, targeting production readiness and market release.\nPartner in Task 2\, O2.3: Breaking the limits: Realizing most advanced GaN HEMT device and integration concepts\nSenior Program Manager responsible for leading Corintis contribution on demonstrating value of topology optimized cooling for future high power (data center applications) GaN modules.\n\n\nAcademic Background\nPhD in Electrotechnics from TU Vienna (2010)\, focused on optimizing GaN HEMTs. Joined Infineon Austria in 2010 as an early GaN technology development engineer\, working on FEOL development plus wafer- and package-level characterization. From 2015–2020\, I managed the development of the first-generation normally-off high-voltage GaN power devices\, launched as CoolGaN in 2021. Today\, I lead High Voltage GaN Technology Development\, managing a team of 20 engineers.\nGaN power devices\nPhD in Precision Engineering (Cranfield University)\, EPFL; background as Principle Investigator on AI research related to drone GPS free navigation systems\, Corintis related scientific contributions in the area of co-packaged and designed cooling.\n\n\nWhat excites you about the project?\nALL2GaN excites me because it’s about speeding up real GaN adoption\, giving engineers practical tools and support to integrate GaN across major applications faster and at scale. That’s the kind of push that can make GaN the next mainstream power semiconductor\nTo develop technologies that can reveal the true capabilities of GaN\nThe opportunity to enable higher-efficiency power electronics for future data centers by integrating advanced microfluidic cooling directly into next-generation GaN power modules.\n\n\nWhat is the biggest challenge in making power electronics greener? [nbsp]\nThe biggest challenge is getting GaN into real products at scale\, making sure it’s reliable in the field\, cost-competitive\, and the supply chain can actually support volume. That’s when “greener” savings become real.\nTo make full use of the GaN properties\nManaging rising heat flux while ensuring efficiency\, reliability\, and scalable manufacturing.\n\n\nLinkedIn\nhttps://www.linkedin.com/in/gianmauro-pozzovivo-66a99a26/ \nhttps://www.linkedin.com/in/elison-matioli-74ab1586/  \nhttps://www.linkedin.com/in/iordan-doytchinov-21b18045/
URL:https://czechsemiconductorcentre.cz/event/invitation-to-the-webinar4-all2gan-insights-driving-greener-power-electronics/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/12/shutterstock_2501790583-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260505
DTEND;VALUE=DATE:20260507
DTSTAMP:20260923T184910
CREATED:20260311T112857Z
LAST-MODIFIED:20260311T112933Z
UID:2098-1777939200-1778111999@czechsemiconductorcentre.cz
SUMMARY:Power Semiconductor Devices & Technologies | ECPE Tutorial | ONLINE
DESCRIPTION:The tutorial is aimed at engineers who are engaged in power electronics and want to improve their knowledge and understanding of power devices including the developments expected in near future. \nThe course starts with a general overview on required power device properties and a very basic treatment of semiconductor material and device physics. Blocking capability of the devices\, unipolar and bipolar current transport and gate control will be discussed. Diodes\, MOS transistors (including compensated superjunction MOS) and Insulated Gate Bipolar Transistors (IGBT) will be treated in detail including their dynamical properties\, safe operation and temperature limits. The wide bandgap semiconductor materials silicon carbide and gallium nitride have become important competitors to silicon. Their superior properties for application and the expectations for the next years will be discussed. Also\, issues concerning control\, packaging and integration will be treated in the corresponding contributions. The following chapters demonstrate basic principles of power electronic systems and the basics of intelligent IGBT / MOSFET control circuits. MOS transistor and IGBT gate drivers for various fields of application are discussed in detail. Finally a short overview of hybrid power electronic integration and the most relevant aspects (cooling\, reliability and EMC problems) will be presented. \n  \n\n\n\n\n\n\n\nDate: 05/05/2026 – 06/05/2026 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nLocation: Digital Event \n\n\n\n\n\n\n\n\n\n\n\n\n\n\nTechnical Chair: \nDr. Anton Mauder\, Infineon Technologies (DE)\nProf. Nando Kaminski\, University of Bremen (DE) \n\nECPE Contact:\nMarietta Di Dio\n+49 911 81 02 88 – 13\nmarietta.didio@ecpe.org \n\nRegistration Deadline: 28 April 2026
URL:https://czechsemiconductorcentre.cz/event/power-semiconductor-devices-technologies-ecpe-tutorial-online/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-11-122756.png
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260427
DTEND;VALUE=DATE:20260430
DTSTAMP:20260923T184910
CREATED:20260316T101745Z
LAST-MODIFIED:20260316T101745Z
UID:2139-1777248000-1777507199@czechsemiconductorcentre.cz
SUMMARY:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
DESCRIPTION:We invite you to attend the 29th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2026)\, which will take place 27–29 April 2026 in Bratislava\, Slovakia. \nDDECS is a well-established international forum bringing together researchers and industry experts working on the design\, verification\, testing\, reliability\, and security of electronic circuits and systems. The programme features keynote talks\, technical sessions\, tutorials\, and networking opportunities covering topics such as digital design\, hardware accelerators\, analog circuits\, AI hardware\, and system reliability. \nOne of the highlights of this year’s programme will be the keynote presentation on 29 April 2026: Karel Masařík\, Director of the Czech Semiconductor Centre \nThis keynote will address the growing complexity of electronic design automation (EDA) and the strategic role of semiconductor technologies in Europe. \nWe warmly invite researchers\, engineers\, students\, and industry partners to join this event and engage with the international microelectronics community. \nMore information and registration are available at:https://deimos.fei.stuba.sk/projekty/DDECS2026/
URL:https://czechsemiconductorcentre.cz/event/ieee-international-symposium-on-design-and-diagnostics-of-electronic-circuits-and-systems/
LOCATION:Bratislava\, Bratislava\, Slovakia (Slovak Republic)
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-16-102601.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260424T100000
DTEND;TZID=Europe/Prague:20260424T120000
DTSTAMP:20260923T184910
CREATED:20260408T075305Z
LAST-MODIFIED:20260408T075313Z
UID:2191-1777024800-1777032000@czechsemiconductorcentre.cz
SUMMARY:Workshop - Photonics Call in Chips JU 2026
DESCRIPTION:Chips JU 2026 Call: Reinforcing Europe’s Strength in PhotonicsOnline | 24 April 2026 | 10:00–12:00 CET \nWe invite you to join an Information and Matchmaking Workshop dedicated to the upcoming Chips Joint Undertaking (Chips JU) 2026 call on photonics. \nThis online session offers a valuable opportunity to gain first-hand insights into the call and to connect with potential partners for future project collaborations. \n\nAbout the Workshop\nThe workshop is designed to support the photonics community in developing high-quality project proposals by providing detailed guidance on the funding call and facilitating networking among stakeholders. \nParticipants will benefit from: \n\nDirect insights into the call from the European Commission and Chips JU representatives\nA dedicated Q&A session addressing key aspects of the call\nPresentations of project ideas from across the community\nPartner search pitches to help build strong consortia\n\nIf you are interested in presenting your project idea\, you are encouraged to get in touch with the organisers. \n\nWhy Attend?\n\nGain a clear understanding of the Chips JU 2026 photonics call\nIdentify potential collaborators and consortium partners\nPosition your organisation for successful proposal development\nStay informed about the latest priorities in European photonics funding\n\n\nFunding Call Overview\nThe HORIZON-JU-Chips-2026-FT2-IA call focuses on reinforcing Europe’s leadership in photonics through innovation-driven projects. \n\nFunding type: Innovation Action (IA)\nEU budget: €20 million (with additional national co-funding)\nExpected projects funded: 2\nSubmission deadline: 17 September 2026\n\nSelected projects are expected to deliver industrial-grade demonstrators of advanced photonic technologies\, demonstrating scalability\, reliability and integration readiness at TRL 7–8. \nKey areas of focus include: \n\nScaling of wafer-level photonic processes\nDevelopment of packaging and testing solutions\nIntegration of heterogeneous materials and components\nCo-optimisation of design and process equipment\nDemonstration of system-level functionality\n\n\nRegister Now\nSecure your place and take the first step towards building strong\, competitive proposals in photonics.
URL:https://czechsemiconductorcentre.cz/event/workshop-photonics-call-in-chips-ju-2026/
LOCATION:on-line
CATEGORIES:External Event
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260421T130000
DTEND;TZID=Europe/Prague:20260421T140000
DTSTAMP:20260923T184910
CREATED:20260407T115750Z
LAST-MODIFIED:20260407T115750Z
UID:2184-1776776400-1776780000@czechsemiconductorcentre.cz
SUMMARY:Chips Think Tank Webinar
DESCRIPTION:We are pleased to invite you to our upcoming Chips Think Tank webinar\, taking place on 21 April at 13:00 CET. \nAs artificial intelligence continues to scale rapidly\, the limitations of traditional electronic architectures are becoming increasingly evident. Photonics is emerging as a key enabler to address these challenges—but how are investors positioning themselves\, and where do the most promising opportunities lie? \nJoin us for an insightful session exploring the investment dynamics shaping the photonics ecosystem. \nWe are delighted to welcome Pieter Klinkert\, Partner and Co-founder of PhotonVentures\, who will share his perspective on: \n\nThe investment thesis behind a venture capital firm fully dedicated to photonics\nHow the most promising start-ups are identified within a highly technical field\nThe impact of AI on the growing demand for optical interconnect technologies\nHow investors anticipate and position themselves in a fast-evolving market\n\nThe session will be hosted by Régis Hamelin\, CTO of BLUMORPHO and Coordinator of aCCCess\, and will include a live Q&A. \n👉 Register here to secure your place:https://www.blumorpho.com/webinar/?webinarKey=8236940136715699552 \nWe encourage you to join the discussion and share this invitation within your networks. \nMore information on aCCCess website: https://www.acccess.eu/events/chips-think-tank-webinar-6 
URL:https://czechsemiconductorcentre.cz/event/chips-think-tank-webinar/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/04/Chips-Think-Tank-200125-5.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260402T180000
DTEND;TZID=Europe/Prague:20260402T220000
DTSTAMP:20260923T184910
CREATED:20260309T095336Z
LAST-MODIFIED:20260309T102601Z
UID:2083-1775152800-1775167200@czechsemiconductorcentre.cz
SUMMARY:Czech Premiere of the Documentary A Chip Odyssey
DESCRIPTION:The Taiwanese documentary A Chip Odyssey will have its Czech premiere in Brno on Thursday\, 2 April at 18:00\, at Kino Lucerna. \nDirected by award-winning filmmaker Hsiao Chu-Chen\, the feature-length documentary tells the remarkable story of how Taiwan built one of the world’s most important semiconductor industries from the ground up. Through interviews with pioneering engineers\, technicians\, policymakers and a new generation of innovators\, the film traces a fifty-year journey that transformed a small island into a global technological powerhouse. \nDrawing on rare archival materials and insights from more than 80 key figures\, A Chip Odyssey reveals the human stories behind the chips that power today’s digital world—from smartphones to artificial intelligence and advanced technologies. The film highlights the courage\, ambition and collective determination that shaped Taiwan’s rise at the centre of the global semiconductor ecosystem. \nScreening details \n\n\nFilm: A Chip Odyssey (2025) (more information on the website) \n\n\nDate: Thursday\, 2 April \n\n\nTime: 18:00 \n\n\nVenue: Kino Lucerna\, Brno \n\n\nJoin us for the Czech premiere of this compelling documentary and discover the extraordinary human story behind one of the most strategic industries of our time.
URL:https://czechsemiconductorcentre.cz/event/czech-premiere-of-the-documentary-a-chip-odyssey/
LOCATION:kino Lucerna\, Brno\, Minská 19\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/plakat.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260328T100000
DTEND;TZID=Europe/Prague:20260328T150000
DTSTAMP:20260923T184910
CREATED:20260214T140336Z
LAST-MODIFIED:20260214T140747Z
UID:2033-1774692000-1774710000@czechsemiconductorcentre.cz
SUMMARY:Days of Electron Microscopy
DESCRIPTION:We warmly invite you to the Days of Electron Microscopy in Brno\, a city-wide celebration of science and discovery\, which this year for the first time includes the Faculty of Electrical Engineering and Communication at Brno University of Technology & Czech Semiconductor Centre. Join us to explore the micro-world and discover what modern science can image\, measure and truly understand. \nSaturday 28 March 2026FEEC BUT\, Technická 8\, Brno10:00–12:00 and 13:00–15:00 \nBrno is recognised as a global leader in electron microscopy\, building on the legacy of Armin Delong. This year marks the 75th anniversary of the first Czechoslovak electron microscope\, constructed in Brno under his leadership — a milestone that helped shape the city’s international reputation in this field. Currently\, every third electron microscope in the world is manufactured in Brno. \n\nProgramme at FEEC BUT\n1) Guided Tour of the Electron Microscope\n(30 minutes – registration required) \nIn laboratory\, specialist Nikola Papež will demonstrate the practical use of an electron microscope. Visitors will observe extreme magnifications and details invisible to the naked eye — such as a nanofibre nearly 1\,000 times thinner than a human hair or a damaged silver contact on the surface of a solar cell. \nParticipation is possible upon prior registration only. \n\n2) Chips and Semiconductors: How the Modern World Is Built\n(No registration required) \nWhat exactly is a semiconductor? How is a microchip manufactured? And why can we not build an electron microscope without chips — nor chips without an electron microscope? \nThis accessible and engaging session will explain the fundamentals of semiconductor technology and its crucial role in modern science and industry. Visitors will see real examples and gain insight into how chips are designed\, fabricated and analysed. \nThe session will be delivered by: \n\n\nJana Drbohlavová\, Coordinator and Deputy Director of the Czech Semiconductor Centre (CSC) \n\n\nMartin Balabán from the student creative team SPICE \n\n\nThe Czech Semiconductor Centre plays a key role in strengthening the Czech Republic’s position in the global semiconductor ecosystem. This part of the programme offers a unique opportunity to understand how advanced research\, industry collaboration and education come together to shape the future of microelectronics — and why semiconductors are strategic for Europe’s technological sovereignty. \nThis session is open to all visitors without registration. \n\nThe event is organised by the Institute of Physics FEEC BUT\, the Department of Microelectronics FEEC BUT\, the Czech Semiconductor Centre (CSC)\, and the student creative team SPICE. We look forward to welcoming curious visitors of all ages — students\, parents and children alike. \nFull programme of the Days of Electron Microscopy Brno:https://dembrno.cz/
URL:https://czechsemiconductorcentre.cz/event/days-of-electron-microscopy/
LOCATION:FEEC\, BUT\, Technická 8\, Brno\, Czech Republic
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/02/Elektronova-mikroskopie3-scaled.jpg
ORGANIZER;CN="CSC":MAILTO:info@czechsemiconductorcentre.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260317
DTEND;VALUE=DATE:20260320
DTSTAMP:20260923T184910
CREATED:20260311T112332Z
LAST-MODIFIED:20260311T112332Z
UID:2090-1773705600-1773964799@czechsemiconductorcentre.cz
SUMMARY:AMPER 2026
DESCRIPTION:From 17–19 March 2026\, the AMPER 2026 trade fair will bring together manufacturers\, developers\, researchers\, startups\, and technology companies from across the electronics\, energy\, and advanced technology sectors at Veletrhy Brno\, a. s. With 400+ exhibitors from more than 20 countries and over 26\,000 visitors\, AMPER ranks among the largest and most influential technology events of its kind in Central Europe. \nFor the semiconductor and chip sector\, events like AMPER play a particularly important role. They create a space where research\, industry and emerging talent meet\, helping to accelerate the transfer of ideas into real-world technologies. As Europe works to strengthen its semiconductor capabilities and resilience of the chip supply chain\, collaboration across universities\, startups\, SMEs and established companies is more important than ever. AMPER provides exactly this kind of environment — bringing together innovators working on electronics design\, embedded systems\, advanced manufacturing\, power electronics\, and the broader technologies that enable the semiconductor value chain. \nThe Czech Semiconductor Centre will be there as well. \nYou can meet our team at the AMPER Innovation Hub in Pavilion P\, where we will be part of exhibitions hosted by our members:\n🔹 Brno University of Technology (Vysoké učení technické v Brně)\n🔹 Czech Technical University in Prague (České vysoké učení technické v Praze) \nWe look forward to meeting startups\, SMEs\, students\, researchers and industry partners who are interested in the future of chips in Europe. Whether you are working on semiconductor design\, advanced electronics\, or exploring collaboration opportunities\, come and say hello. \nLet’s talk about talent\, innovation\, and how we can strengthen the semiconductor value chain in Czechia and across the European Union.
URL:https://czechsemiconductorcentre.cz/event/amper-2026/
LOCATION:Brno\, Božetěchova 1/2\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/uz.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260317
DTEND;VALUE=DATE:20260319
DTSTAMP:20260923T184910
CREATED:20260311T112636Z
LAST-MODIFIED:20260311T112659Z
UID:2093-1773705600-1773878399@czechsemiconductorcentre.cz
SUMMARY:Gate Drivers and Control Circuitry of IGBTs and MOSFETs
DESCRIPTION:Gate Drivers and control circuits are the interface between the signal level and the power stage within a power electronic system. They are responsible for a safe operation of the power switches. \nThe development of gate driving circuits for ideal operation of power electronics necessitates profound knowledge of semiconductor characteristics (MOSFETs\, IGBTs)\, influence of gate voltage on switching behaviour\, power supply of galvanically isolated parts of the circuitry\, parasitics\, and protection functions. \nBeginning with silicon MOSFETs\, switching behaviour will be explained\, and then derived for Silicon Carbide MOSFETs and IGBTs. As the mechanisms are basically the same for all voltage/power classes\, no differentiation will be done between high and low power devices. \nIn the context of the development and adoption of innovative Wide-Band-Gap semiconductors\, new challenges concerning robust operation at very fast switching speed and frequencies are also addressed to attain the expected gains at system level. \nWith this tutorial we want to transfer the necessary knowledge to drive and control IGBTs and MOSFETs in a safe way. The focus is on modules\, discretes will be covered only briefly.
URL:https://czechsemiconductorcentre.cz/event/gate-drivers-and-control-circuitry-of-igbts-and-mosfets/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-11-122452.png
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260310
DTEND;VALUE=DATE:20260313
DTSTAMP:20260923T184910
CREATED:20251201T144124Z
LAST-MODIFIED:20251201T144225Z
UID:1789-1773100800-1773359999@czechsemiconductorcentre.cz
SUMMARY:Embedded World 2026
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management.
URL:https://czechsemiconductorcentre.cz/event/embedded-world-2026/
LOCATION:Nuremberg\, Nuremberg\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/12/embedded-n-dynamicteaser-eingangsbereich.webp
END:VEVENT
END:VCALENDAR