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DTSTART;VALUE=DATE:20260317
DTEND;VALUE=DATE:20260319
DTSTAMP:20260923T211052
CREATED:20260311T112636Z
LAST-MODIFIED:20260311T112659Z
UID:2093-1773705600-1773878399@czechsemiconductorcentre.cz
SUMMARY:Gate Drivers and Control Circuitry of IGBTs and MOSFETs
DESCRIPTION:Gate Drivers and control circuits are the interface between the signal level and the power stage within a power electronic system. They are responsible for a safe operation of the power switches. \nThe development of gate driving circuits for ideal operation of power electronics necessitates profound knowledge of semiconductor characteristics (MOSFETs\, IGBTs)\, influence of gate voltage on switching behaviour\, power supply of galvanically isolated parts of the circuitry\, parasitics\, and protection functions. \nBeginning with silicon MOSFETs\, switching behaviour will be explained\, and then derived for Silicon Carbide MOSFETs and IGBTs. As the mechanisms are basically the same for all voltage/power classes\, no differentiation will be done between high and low power devices. \nIn the context of the development and adoption of innovative Wide-Band-Gap semiconductors\, new challenges concerning robust operation at very fast switching speed and frequencies are also addressed to attain the expected gains at system level. \nWith this tutorial we want to transfer the necessary knowledge to drive and control IGBTs and MOSFETs in a safe way. The focus is on modules\, discretes will be covered only briefly.
URL:https://czechsemiconductorcentre.cz/event/gate-drivers-and-control-circuitry-of-igbts-and-mosfets/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-11-122452.png
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260310
DTEND;VALUE=DATE:20260313
DTSTAMP:20260923T211052
CREATED:20251201T144124Z
LAST-MODIFIED:20251201T144225Z
UID:1789-1773100800-1773359999@czechsemiconductorcentre.cz
SUMMARY:Embedded World 2026
DESCRIPTION:The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management.
URL:https://czechsemiconductorcentre.cz/event/embedded-world-2026/
LOCATION:Nuremberg\, Nuremberg\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/12/embedded-n-dynamicteaser-eingangsbereich.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260204
DTEND;VALUE=DATE:20260206
DTSTAMP:20260923T211052
CREATED:20251201T143544Z
LAST-MODIFIED:20251201T143704Z
UID:1783-1770163200-1770335999@czechsemiconductorcentre.cz
SUMMARY:ECS Brokerage Event 2026
DESCRIPTION:Registration is now open for The ECS Brokerage Event\, which will return to Brussels on 4&5 February 2026 at a new venue location; The EGG\, Brussels. The event combines the brokerage activities of the industry associations AENEAS\, EPoSS and INSIDE into one networking event dedicated to project proposals for the new Chips JU Calls 2026. \nThis event gathers the ECS community around project ideas\, allowing it to network\, build consortia and start creating project proposals. We encourage you to plan your travel and accommodation early\, as back-to-back events are scheduled before and after the Brokerage.
URL:https://czechsemiconductorcentre.cz/event/ecs-brokerage-event-2026/
LOCATION:Brussels\, Brussels\, Belgium
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/12/Snimek-obrazovky-2025-12-01-153559.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260125
DTEND;VALUE=DATE:20260131
DTSTAMP:20260923T211052
CREATED:20251002T065847Z
LAST-MODIFIED:20251002T065847Z
UID:1677-1769299200-1769817599@czechsemiconductorcentre.cz
SUMMARY:The FAMES European FD-SOI Design School (EFDS)
DESCRIPTION:The FAMES European FD-SOI Design School (EFDS) is a one-week theoretical and practical training course focused on FD-SOI design. \n\nDate: From Jan. 25 to 30\, 2025\nLocation: CIME Nanotech and CEA-Leti\, Grenoble\, France\n\nThis course is intended for chip designers\, engineers\, Masters and PhD students\, with the purpose of providing the essential scientific and technical foundations for developing integrated circuits using FD-SOI technology. \nThe comprehensive program includes important topics such as transistor modeling\, sophisticated analog and RF design techniques (including body-biasing)\, the complete digital circuit design flow (from RTL to routing)\, and crucial design-for-test methodologies. The curriculum combines expert lectures with hands-on sessions to give participants a practical learning experience. \nThis winter school represents a key opportunity to strengthen expertise within the European FD-SOI ecosystem and empower the next generation of designers. \nIf you are interested in participating\, we would be delighted to welcome you or your colleagues to this training. Please note that places are limited and that all the details (including prerequisites) are available on our website.
URL:https://czechsemiconductorcentre.cz/event/the-fames-european-fd-soi-design-school-efds/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/10/x.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260115
DTEND;VALUE=DATE:20260116
DTSTAMP:20260923T211052
CREATED:20251205T093721Z
LAST-MODIFIED:20251205T094005Z
UID:1798-1768435200-1768521599@czechsemiconductorcentre.cz
SUMMARY:Get Spin-off/Start-up Ready!
DESCRIPTION:Turn your research into real-world impact\nScience can change the world — when it reaches beyond the university walls. It is our mission at CTU Technology Transfer to support you in turning your idea/research into a university spin-off or an independent startup. \nJoin our semestral Spin-off/Start-up Ready! program to put on the business hat\, understand the journey to commercialization\, practice the use of vital business tools\, and build a network of investors and industry partners to bring your innovation to life! \n\n\nWho can join?\nReady! is open to all CTU students\, PhD candidates\, postdocs\, and researchers – Czech and international – who want to explore the business potential of their ideas. \nThe program runs in English. 16 participants will be accepted to ensure individual mentoring and a highly practical experience. \n\n\nProgram at a glance\n\n\nDuration\nFebruary – June 2026 \n\n\nFormat\nIn-person\, Thursdays 9:00–12:30 (incl. brunch) \n\n\nLocation\nPrague \n\n\nLanguage\nEnglish \n\n\nApplication deadline\n15 January 2026 \n\n\nFinal pitch night\n4 June 2026 \n\n\n\nParticipation fee\nParticipation free of charge \n\n\n\nParticipants get\n\nKnow-how & practice in 8 key commercialization steps + final investor pitch\nPractical assignments to develop their own idea/research\nDedicated business mentoring: each participant is matched with an experienced mentor who supports them individually throughout the program and helps them achieve quality outcomes on the practical assignments between workshops (for participant’s real project)\nNetworking with business community and investors\nČVUT microcertificate upon completion\nFurther commercialization support with contracts\, legal issues\, patents\, incubation\, etc.\n\n\n\nWhat makes Ready! different\n\nHigh-value workshops: expert faculty\, small cohort (max. 16 participants)\nPractical focus: 70% of your time spent developing your own research-to-business idea\nIndividual business mentoring: each participant/team works with an experienced business mentor\nEssential business & soft skills: validation of commercial potential\, business and financial plan\, go-to-market strategy\, team composition and management\, IP protection\, legal support\, pitching to investors\nCommunication for impact: short and intense communication practice spread over all workshops to build you as a strategic\, structured and confident presenter of your business ideas\nBusiness contacts: establishing relationships with topic experts\, business mentors\, industrial partners\, and investors\nSupport beyond the program: guidance\, legal counsel and incubation by ČVUT Technology Transfer seamlessly following the Ready! program\n\n\n  \nReady flyer
URL:https://czechsemiconductorcentre.cz/event/1798/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/12/Snimek-obrazovky-2025-12-05-103732.png
ORGANIZER;CN="FEE CTU":MAILTO:xprajzlv@fel.cvut.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251203
DTEND;VALUE=DATE:20251205
DTSTAMP:20260923T211052
CREATED:20250710T114355Z
LAST-MODIFIED:20250710T114355Z
UID:1533-1764720000-1764892799@czechsemiconductorcentre.cz
SUMMARY:EFECS 2025
DESCRIPTION:The next edition of EFECS – the European Forum for Electronic Components and Systems is taking place in Malta\, on December 3–4\, 2025\, at the Hilton Hotel in St. Julian’s – the very same place where the journey began with the 1st ECSEL Symposium 2017 that set the course for the ECS community in Europe. This year’s theme\, Accelerate Innovation: Building European Competitiveness\, puts the spotlight on value chain security\, sustainability\, and emerging market opportunities\, all in the context of Europe’s strategic drive for technological sovereignty. \n💡 Why Attend EFECS 2025? \n\nInsightful keynotes & discussions on cutting-edge topics like quantum tech\, cybersecurity\, AI\, and more.\nNetworking with 700+ stakeholders from across Europe’s semiconductor and ECS ecosystem.\nStrengthening the Chips Joint Undertaking mission: Learn how Europe is advancing semiconductor leadership and resilience.\nCelebrating progress and contributing to the future direction of the Chips Joint Undertaking and the broader ECS value chain.\n\nRegistration opens soon – mark your calendars and stay tuned for more details!
URL:https://czechsemiconductorcentre.cz/event/efecs-2025/
LOCATION:Hilton Hotel\, St Julian’s\, Malta\, Vjal Portomaso\, St. Julian´s\, PTM01\, Malta
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/Snimek-obrazovky-2025-07-10-134237.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251127
DTEND;VALUE=DATE:20251128
DTSTAMP:20260923T211052
CREATED:20251002T065344Z
LAST-MODIFIED:20251002T065344Z
UID:1672-1764201600-1764287999@czechsemiconductorcentre.cz
SUMMARY:DC Circuit Breaker - Technologies and Applications
DESCRIPTION:With the rapid move towards DC grids for efficient integration of renewables and storage\, protection technologies are becoming critical. This workshop explores the role of DC circuit breakers – with a focus on solid-state solutions using advanced SiC devices – to ensure fast\, reliable fault protection. Featuring leading experts from Europe and Japan\, the event will highlight the latest research and applications shaping the future of DC power systems. \nECPE Online Workshop\nDC Circuit Breaker – Technologies and Applications \n27 November 2025 online \nDC grids use direct current for power distribution\, offering greater efficiency and cost-effectiveness in the growing decentralized energy landscape\, particularly for integrating renewable energy sources like solar photovoltaics and battery storage. Unlike the conventional AC grid\, DC grids eliminate inefficient conversion steps\, as many modern devices and energy sources are inherently DC-powered. This trend to DC grids\, particularly in the Medium Voltage (MV) range\, leads to a similar challenge as in vehicle electrification with on-board voltages of 800 V in EVs and > 1000 V in heavy duty vehicles\, the DC Circuit Breaker (DC-CB) issue. As a protection element the DC-CB has to open very fast in case of a fault e.g. a short circuit\, and in on-state lowest losses are key. Solid-State Circuit Breakers (SSCBs) are protection devices that use power semiconductors (Si-MOSFETs or IGBTs\, or SiC transistors)\, instead of mechanical contacts to safeguard electrical circuits against overloads and short circuits\, allowing an extremely fast interruption in a few microseconds. These requirements make fast-switching SiC devices with its low on-resistance an excellent choice for Solid-State Circuit Breakers. \nFurthermore\, the workshop aims to strengthen the cooperation between Europe and Japan in the area of SiC-based Circuit Breaker research. Therefore\, Prof. Keiji Wada from the Tokyo Metropolitan University has been invited to join the team of Technical Chairs with Prof. Brueckner (Bundeswehr University Munich) and Prof. Lorenz (ECPE). \nRegistration Deadline: 20 November 2025 \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nProgramme in PDF here. \n 
URL:https://czechsemiconductorcentre.cz/event/dc-circuit-breaker-technologies-and-applications/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/10/Snimek-obrazovky-2025-10-02-085312.png
ORGANIZER;CN="ECPE":MAILTO:svenja.roth@ecpe.org
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251118
DTEND;VALUE=DATE:20251122
DTSTAMP:20260923T211052
CREATED:20250509T105833Z
LAST-MODIFIED:20250509T105833Z
UID:1355-1763424000-1763769599@czechsemiconductorcentre.cz
SUMMARY:SEMICON Europa 2025
DESCRIPTION:SEMICON Europa 2025 is co-located with productronica and will take place in November 18-21\, 2025 in Munich\, Germany. This year’s theme Global Collaborations for European Economic Resilience expresses that global collaborations are not just beneficial for Europe’s resilience\, they are essential. In today’s interconnected world\, Europe cannot afford to operate in isolation. By working closely with other nations\, Europe can safeguard its prosperity\, sustainability\, and security for future generations. \nThis approach will enable the industry to create a future where technological innovations and environmental sustainability thrive together. \n– Top-notch Keynotes\n– Market Trends\n– Exhibition\n– Networking\n– Advanced Packaging Forum / Fab Management Forum\n– Sustainability\n– Smart Manufacturing / Mobility / MedTech\n– Workforce Development and many more!
URL:https://czechsemiconductorcentre.cz/event/semicon-europa-2025/
LOCATION:München\, München\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/Snimek-obrazovky-2025-05-09-125538.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251023
DTEND;VALUE=DATE:20251025
DTSTAMP:20260923T211052
CREATED:20250619T142332Z
LAST-MODIFIED:20250619T142605Z
UID:1508-1761177600-1761350399@czechsemiconductorcentre.cz
SUMMARY:IMAPS 2025 flash Conference
DESCRIPTION:The conferences organized by IMAPS Czech and Slovak Republic Chapter typically focus on current trends\, challenges\, and innovations in microelectronics\, packaging technologies\, and the manufacturing and protection of electronic assemblies. These events bring together professionals from academia\, industry\, and R&D to exchange knowledge\, present new developments\, and foster collaboration. \nThe IMAPS CZ a SK\, as part of the international IMAPS organization\, promotes the advancement of microelectronics and packaging technologies through conferences\, workshops\, and networking. It supports education\, research\, and the dissemination of technical knowledge in the fields of electronics manufacturing\, design\, materials\, and reliability. \nTopics from previous years: \n\nTrends in wireless technologies from the perspective of international distributors\nDesign for manufacturability in modern electronics\nImproving the cleaning process of electronic assemblies through better design\nCorrosion protection of PCBs\nApplication of XRF (X-ray fluorescence) in production control\nHidden risks in the repair of long-lifecycle electronic systems\nHigh-precision measurement using FBG-based sensors\nNew requirements for capacitors and passive components\nVerification of soldering in surface mount technology for space applications\nCurrent state and trends in EDA (Electronic Design Automation) software\n\n  \nIMAPS flash Conference is the European forum for the exchange of information between senior and young scientists from academic communities and electronic industries on topics related to their experimental and theoretical work in the very wide-spread field of electronics\, microelectronic technology and packaging. \nIt is our pleasure to encourage you to participate in IMAPS flash Conference 2025 “Quantum meets silicon”\, organized by International Microelectronics and Packaging Society Czech and Slovak Chapter (IMAPS CZ&SK)\, Brno University of Technology (BUT) and Institute of Scientific Instruments (ISI). \n+ Workshop on quantum technologies in semiconductors (The year 2025 has been proclaimed by the United Nations as the International Year of Quantum Science and Technology. The aim of this initiative is to raise awareness of the contributions of quantum mechanics and quantum materials to science\, industry\, and everyday life\, in connection with the 100th anniversary of the formulation of quantum mechanics.) \nWe will meet in one of Brno’s iconic villas. The evening will be accompanied by swing music (The Friday Swingers). You will enjoy good food\, drinks and fruitful conversations. We are looking forward to meeting you all.
URL:https://czechsemiconductorcentre.cz/event/imaps-2025-flash-conference/
LOCATION:Institute of Scientific Instruments of the Czech Academy of Sciences\, Královopolská 147\, Brno\, 61200\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/06/Z5he8s9E.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20251022T090000
DTEND;TZID=Europe/Prague:20251022T160000
DTSTAMP:20260923T211052
CREATED:20251009T074548Z
LAST-MODIFIED:20251009T074548Z
UID:1680-1761123600-1761148800@czechsemiconductorcentre.cz
SUMMARY:Re-Thinking Electronics – Is Greentech Too Good to Be True?
DESCRIPTION:The workshop Re-Thinking Electronics – Is Greentech Too Good to Be True? will take place in Prague on October 22 from 9:00 a.m. to 4:00 p.m. at the Vienna House Diplomat. \nWe invite partners from European projects on sustainable electronics to attend the workshop. You can look forward to the participation of experts from research centers and incubators (VTT\, TNO\, Fraunhofer)\, as well as industry players (Covestro\, Flexoo\, BD Medical). \nTopics will include:\n• the use of printed and flexible electronics technologies\n• precious metal waste management strategies\n• the development of compostable electronic components\n• the practical implementation of circular policies \nMore information about the event\, including the program and registration\, can be found HERE. \nJoin us for a full-day free-of-charge forum exploring the realities of sustainable electronics – from bold innovations to hard truths. This full-day event will bring together top minds from across Europe – spanning industry\, academia\, policy\, and research.
URL:https://czechsemiconductorcentre.cz/event/re-thinking-electronics-is-greentech-too-good-to-be-true/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/10/x.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251021
DTEND;VALUE=DATE:20251024
DTSTAMP:20260923T211052
CREATED:20250910T070708Z
LAST-MODIFIED:20250910T070708Z
UID:1630-1761004800-1761263999@czechsemiconductorcentre.cz
SUMMARY:BioChip and Biomedicine Chip Design
DESCRIPTION:Discover the future of biochips and biomedical chip technologies at this unique international event\, taking place in Brno and online on October 21–23\, 2025. The program brings together researchers from Taiwan\, Korea\, Japan\, and the Czech Republic to share the latest advances in diagnostics\, wearable electronics\, olfactory sensing\, microfluidics\, and biochip applications. \nParticipants will gain insights into cutting-edge topics such as nanoengineered platforms for rapid disease diagnostics\, electronic fibers for smart garments\, olfactory sensors\, smartphone-based health monitoring\, point-of-need microfluidic devices\, and two-photon lithography for advanced biochip fabrication. Alongside inspiring lectures\, the program will also feature hands-on laboratory sessions on microfluidics\, wearable sensors\, and mobile health applications. The event offers not only expert talks and practical demonstrations\, but also an optional excursion to IQS nano\, networking opportunities\, and a guided tour of Brno. \nDon’t miss the chance to connect with leading experts and explore how biochip innovations are shaping the future of healthcare\, wearable electronics\, and diagnostics. \nThe capacity of the event is limited. We recommend to register as soon as possible. \nLaboratory exercises\nMicrofluidics (Dr. Ludovico Magliaccio – Brno University of Technology)\n\nThis session will demonstrate how to design and fabricate microfluidic chips quickly\, cost-effectively\, and with minimal equipment. The focus will be on practical method for rapid prototyping\, along with a simple setup for testing and operating the fabricated chips. \nSmartphone application for cardio features estimation (Dr. Andrea Němcová – Brno University of Technology) \nDevelopment of smartphone application „Tepovka“ for cardio features estimation will be described from the perspective of sensors\, app development\, algorithm\, accuracy and future outlook. It will be enriched with a real demonstration\, approx. 15-20 min. \nWearable sensors (Prof. Jaromír Hubálek\, Dr. Jakub Arm) \nVitality assessment via wearable activity monitoring will present a sensor system incorporating data fusion\, activity recognition\, energy expenditure estimation\, and vitality assessment (poster). This will be complemented by a live demonstration with an Android application on a treadmill\, and by measuring salinity. \nAll details with registration is available here.
URL:https://czechsemiconductorcentre.cz/event/biochip-and-biomedicine-chip-design/
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/09/b.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251020
DTEND;VALUE=DATE:20251023
DTSTAMP:20260923T211052
CREATED:20250724T114730Z
LAST-MODIFIED:20250724T114810Z
UID:1556-1760918400-1761177599@czechsemiconductorcentre.cz
SUMMARY:European Conference on EDGE AI Technologies and Applications – EEAI
DESCRIPTION:Join the 𝗘𝘂𝗿𝗼𝗽𝗲𝗮𝗻 𝗖𝗼𝗻𝗳𝗲𝗿𝗲𝗻𝗰𝗲 𝗼𝗻 𝗘𝗗𝗚𝗘 𝗔𝗜 𝗧𝗲𝗰𝗵𝗻𝗼𝗹𝗼𝗴𝗶𝗲𝘀 𝗮𝗻𝗱 𝗔𝗽𝗽𝗹𝗶𝗰𝗮𝘁𝗶𝗼𝗻𝘀 (EEAI 2025)\, taking place 20–22 October 2025 in Naples\, Italy. EEAI2025 is the European event dedicated to the entire edge AI ecosystem\, from the foundational edge AI hardware and software to the most advanced algorithms\, agentic AI\, generative AI and applications\, the conference explores the latest breakthroughs. During the event\, you’ll get to explore edge AI\, learn from experts in the field\, network with the community and stay updated on the latest technological innovations. \nℹ️️ More information: https://lnkd.in/dVTHu6eS\n🔗 Register now to secure your spot: https://lnkd.in/exd2MJZ6 \n📧 Are you interested in contributing? Submit your presentation\, paper abstracts or poster by 15 August 2025 to info@edge-ai-tech.eu
URL:https://czechsemiconductorcentre.cz/event/1556/
LOCATION:Naples\, Italy\, Naples\, Italy
CATEGORIES:External Event
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ORGANIZER;CN="EdgeAI":MAILTO:info@edge-ai-tech.eu
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251011
DTEND;VALUE=DATE:20251013
DTSTAMP:20260923T211052
CREATED:20250918T124623Z
LAST-MODIFIED:20250918T124750Z
UID:1648-1760140800-1760313599@czechsemiconductorcentre.cz
SUMMARY:Open Days in onsemi Czechia (Rožnov)
DESCRIPTION:Several themed excursions will take you on an exciting journey into the world of chip design and manufacturing\, which powers cars\, smartphones\, and modern industry. We have also prepared a series of entertaining and interactive workshops where you can try your hand at firefighting simulations or first aid “live.” \nThe number of places on individual excursions and workshops is limited. Don’t hesitate and book what interests you in advance using our intuitive booking system. Participation in individual activities may be subject to age restrictions. Please pay attention to the detailed description in the booking system. \nExcursions to learn \nWe will introduce you to the individual stages of semiconductor development and production through four separate engaging excursions. Choose the area that interests you most\, or all of them! \nIn the integrated circuit design center\, you will learn about the environment where engineers transform their ideas into specific integrated circuit designs. This is where the whole story of the digital future begins. (Building C12) \nSilicon wafers are the most commonly used material for chip production. We will also introduce you to their production in detail. (Building M10) \nYou can also explore with us the innovative processes used in the production of silicon carbide wafers\, which we were the first in the world to use on an industrial scale. (Building V1) \nTake a look with us at the individual stages of chip production\, the invisible heroes of our digital age. (Building M8) \nDon’t miss the adrenaline-filled experience of extinguishing a fire and rescuing people from a smoke-filled space. (Building M8) \nLearn how to provide first aid under the guidance of experienced instructors. Virtual reality Human Anatomy will give you a glimpse into the human body. (Building M8) \nYou can test your own health in the interactive Health Day zone with a range of preventive examinations. (Building M8) \nDon’t miss the Škoda EDU.Lab mobile laboratory\, which was created as a unique project by Škoda Auto to support technical education. This specially modified truck will bring samples of the latest technologies used in modern electronics and automobiles\, including robotics\, artificial intelligence\, 3D printing\, and virtual reality\, to Rožnov. \nThe open days at onsemi promise not only a fascinating look behind the scenes of chip production\, but also a rich program of experiences for young and old alike.
URL:https://czechsemiconductorcentre.cz/event/open-days-in-onsemi-czechia-roznov/
LOCATION:onsemi\, Rožnov pod Radhoštěm\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/09/Snimek-obrazovky-2025-09-18-144527.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20251008
DTEND;VALUE=DATE:20251009
DTSTAMP:20260923T211052
CREATED:20250804T092040Z
LAST-MODIFIED:20250804T092129Z
UID:1589-1759881600-1759967999@czechsemiconductorcentre.cz
SUMMARY:EBSCON 2025
DESCRIPTION:Join us for the 5th edition of EBSCON\, the flagship event for professionals\, pioneers\, and visionaries in the electronic and software-based systems industry. Hosted by Silicon Alps Cluster GmbH\, EBSCON 2025 brings together over 350 participants\, including international keynote speakers\, cutting-edge startups\, regional industry leaders\, and innovation-driven public institutions. \nThis Year’s Focus: Creative Destruction\nInspired by economist Joseph Schumpeter\, this year’s theme explores how radical innovation and disruption fuel long-term progress. From AI and sustainability to regional transformation and human-centric tech\, EBSCON 2025 challenges attendees to rethink the future through first principles and bold questions. \nWhat to Expect:\n\n\nOpening Ceremony with political and industry leaders \n\n\nLive signing of a memorandum between European Chips Competence Centers \n\n\nKeynotes\, including a headline talk by Henriette Frädrich: “The Magic of First Principles & Question Marks” \n\n\nInteractive tracks like the Pioneers Pitch\, Bar Camps\, and Panel Discussions \n\n\nStart-up exhibitions\, industry showcases\, and networking lounges \n\n\nFree 1:1 matchmaking via B2Match (slots open one month prior) \n\n\nExtensive media coverage\, including a live press conference and social media features \n\n\n\n\nReady to be part of the change?\nRegistration is free and open now!👉 Find out more information on the event website!
URL:https://czechsemiconductorcentre.cz/event/ebscon-2025/
LOCATION:Messe Congress Graz\, Austria\, Messe Congress\, Graz\, Austria
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/08/IG_8230.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20250929T150000
DTEND;TZID=Europe/Prague:20250929T170000
DTSTAMP:20260923T211052
CREATED:20250910T070042Z
LAST-MODIFIED:20250910T070134Z
UID:1626-1759158000-1759165200@czechsemiconductorcentre.cz
SUMMARY:Heterogeneous Integration in Action: Powering the Next Era of Connectivity
DESCRIPTION:Heterogeneous Integration in Action: Powering the Next Era of Connectivity! \nWith speakers from the EU-funded project HiCONNECTS\, this webinar will provide exclusive insight into the groundbreaking work of over 60 leading companies and institutions advancing high-speed communications technologies across Europe. \nHiCONNECTS – Heterogeneous Integration for Connectivity and Sustainability – is a flagship Chips JU project supporting the EU’s ambition to double its microelectronics industry market share. The consortium is developing next-generation electronic components\, systems\, and integration technologies to power networking and RF innovations such as Wi-Fi\, 5G/6G\, and radar. \nThe project also targets energy-efficient\, sustainable cloud and edge computing platforms\, helping to bring digital services closer to end users. Its work spans high-performance computing\, storage\, networking\, and real-time analysis of IoT sensors and big data. \nWho should attend: \n\nIndustry representatives interested in cutting-edge developments across the ECS value chain\nJunior professionals and students eager to launch a career in Europe’s microelectronics ecosystem\n\nWhen? \n\n September 29\, 2025\n 15:00 CET\n\nLive and On-demand. It is free of charge. \nRegister now!
URL:https://czechsemiconductorcentre.cz/event/heterogeneous-integration-in-action-powering-the-next-era-of-connectivity/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/09/y.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250926
DTEND;VALUE=DATE:20250927
DTSTAMP:20260923T211052
CREATED:20250724T122238Z
LAST-MODIFIED:20250724T123452Z
UID:1562-1758844800-1758931199@czechsemiconductorcentre.cz
SUMMARY:ChipQuest Challenge (SEMI)
DESCRIPTION:Know a student with a creative spark? Invite them to join the ChipQuest Challenge! The ChipQuest Challenge calls on students from 1st grade to university to create a 2 to 5-minute video that explains semiconductors in a fun\, engaging way. Videos should highlight how semiconductors power our everyday lives with facts or demos. The winners will receive a tech device of their choice worth up to 1\,000 EUR! \n💡 Our mission is to spark curiosity in young minds and inspire the next generation of semiconductor talent through creativity and learning.\nJoin us in building the future talent pipeline for the semiconductor industry and help inspire tomorrow’s innovators!\n🔗 Learn more: https://www.semi.org/eu/chipquest \n🌟 Become a sponsoring company!\nBy sponsoring ChipQuest\, companies can:\n✅ Inspire the next generation of semiconductor talent\n✅ Help raise awareness of the industry’s exciting opportunities\n✅ Engage directly with students and future professionals\nSponsors can provide:\n🎁 Cutting-edge tech prize (worth 500–1\,000 EUR)\n🏭 Exclusive company tour\n🎓 One-hour mentorship session with a company expert\n🎟 Four-day pass to SEMICON Europa (provided by SEMI Europe) \nDeadline: Submit your video anytime before September 26\, 2025. Winners will be announced by the end of October 2025.  \nInterested in sponsoring a student? Get in touch with SEMI at chipstalent@semi.org
URL:https://czechsemiconductorcentre.cz/event/chipquest-challenge-semi/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/Snimek-obrazovky-2025-07-24-141906.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20250918T153000
DTEND;TZID=Europe/Prague:20250918T173000
DTSTAMP:20260923T211052
CREATED:20250910T065246Z
LAST-MODIFIED:20250910T065345Z
UID:1623-1758209400-1758216600@czechsemiconductorcentre.cz
SUMMARY:Pre-Brokerage for Lab to Fab Accelerator projects on Advanced Packaging
DESCRIPTION:We kindly invite you to join the Pre-Brokerage for Lab to Fab Accelerator projects on Advanced Packaging \non September 18\, 2025\n15:30 – 17:30 CEST\nin Grenoble\, France\, at the World Trade Center.\n\nThe workshop will take place in conjunction with and is kindly hosted by the EMPC 2025 | The 25th European Microelectronics & Packaging Conference (EMPC 2025). \nChips JU is currently preparing the launch of two calls for Advanced Packaging. The goal of the workshop is to inform the community about the call content and to initiate consortia building. \nThe respective draft call https://www.chips-ju.europa.eu/CallDetails/?id=2af90e5b-d984-f011-b4cc-000d3ab33b4d has been published on September 2\, 2025. \nPlease register here for the workshop: https://pretix.eu/eposs/LabToFab/. The workshop will take place onsite only.
URL:https://czechsemiconductorcentre.cz/event/pre-brokerage-for-lab-to-fab-accelerator-projects-on-advanced-packaging/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/09/x.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20250917T130000
DTEND;TZID=Europe/Prague:20250917T160000
DTSTAMP:20260923T211052
CREATED:20250826T084437Z
LAST-MODIFIED:20250826T151111Z
UID:1603-1758114000-1758124800@czechsemiconductorcentre.cz
SUMMARY:Introduction to services of Czech Semiconductor Centre\, pilot lines and design platform
DESCRIPTION:Come and join us to discover Czech Semiconductor Centre. On-line seminar with introduction to services of Czech Semiconductor Centre\, pilot lines and desigh platform. Lets meet us on Teams on 17th September 2025 from 1PM to 4PM. \nProgramme: \n1:00 p.m. – 1:30 p.m. Introduction to CSC (Karel Masařík\, Director) \n1:30 p.m. – 2:00 p.m. Introduction to the FAMES pilot line (Dominique Noguet\, PhD; FAMES Pilot Line Project Coordinator; CEA-Leti) followed by discussion \n2:00 p.m. – 2:30 p.m. Introduction to the APECS pilot line (Dr.-Ing. Christoph Kroh; Manager Business Development; Fraunhofer Group for Microelectronics | Research Fab Microelectronics Germany (FMD) followed by discussion \n2:30 p.m. – 3:00 p.m. Introduction to Design Platform (Helio Fernandez Tellez\, European Chips Design Platform\, imec) followed by discussion \n3:00 p.m. – 3:45 p.m. Overview of CSC services (presented by Activity coordinators) + “What are your needs” \n3:45 p.m. – 4:00 p.m Closing remarks \nRegistration via Teams here.
URL:https://czechsemiconductorcentre.cz/event/1603/
LOCATION:on-line on Teams
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/08/CSC-seminar-v2.jpg
ORGANIZER;CN="CSC":MAILTO:info@czechsemiconductorcentre.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20250916T090000
DTEND;TZID=Europe/Prague:20250916T123000
DTSTAMP:20260923T211052
CREATED:20250717T110719Z
LAST-MODIFIED:20250728T085927Z
UID:1549-1758013200-1758025800@czechsemiconductorcentre.cz
SUMMARY:Chips JU Workshop on Microelectronics for 6G – Front End Module
DESCRIPTION:The aim of this “Microelectronics for 6G – Front End Module” workshop is to gather detailed feedback about the needs\, challenges and priorities of relevant stakeholders for a Focus Topic under consideration on the FEM extension\, which is a strategic domain for 6G developments. The Focus Topic would also aim at supporting innovation in the sector and would be part of the Chips JU Work Programme 2026 in complement and synergy with the planned FEM activities under the SNS programme. \nThe proposed FEM extension is intended to complement the current FEM call under SNS\, which will not allow to address a complete set of architectural scenarios\, technological assessment and integration of all relevant modules. From the starting point of SNS activities on FEM detailed design for partial FR3 Operations (7-15 GHz)\, a call extension to complement these activities is critical to secure business impact for a European FEM solution targeting 6G FR3. \nAgainst this background\, the FEM extension is expected to: \n\nmature the technology\, with focus on hardware development that may be valorised through IP/PoC developments in the mobile communications context in connection to the system development.\nhigher level of integration compared with the currently open SNS call and going towards TRL 7-8\, and system validation\, moving towards over the air demos (OTA).\n⁠integration aspects should eventually be connected to the APECS pilot line and AAS PoC development.\npossible future Innovation Action(s) (IA) for high TRL level (7-8) aiming towards industrial-scale integration and/or manufacturing.\n\nStructure and expected outcome of the on-line workshop \nThe workshop will be structured in two sessions: the first one centred on FEM semiconductor enabling technologies and R&I requirements that are needed to secure the technological basis to develop a FEM; the second one centred on integration/validation aspects\, PoC developments and pre-industrialisation through use of Pilot lines. \nEach one of them will include: \n\nPresentation of the proposal for FEM extension.\nFeedback from participants (telecoms and microelectronics industry representatives\, RTOs).\nViews of the Chips JU industrial associations (AENEAS\, EPoSS\, INSIDE) and of Participating States.\nWrap up and conclusions focusing on the elements needed for a draft focus topic on a FEM extension.\n\nRegistration here. \nMore details here in document.
URL:https://czechsemiconductorcentre.cz/event/chips-ju-workshop-on-microelectronics-for-6g-front-end-module/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/Snimek-obrazovky-2025-07-28-105905.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250912
DTEND;VALUE=DATE:20250913
DTSTAMP:20260923T211052
CREATED:20250724T123746Z
LAST-MODIFIED:20250724T123746Z
UID:1566-1757635200-1757721599@czechsemiconductorcentre.cz
SUMMARY:Join the EU Business Hub Missions to Japan & Korea! Deadline 12 September.
DESCRIPTION:The EU Business Hub\, an EU-funded programme supporting the international expansion of European SMEs and start-ups\, is pleased to invite companies active in the semiconductor sector to apply for two upcoming business missions to Japan and the Republic of Korea. These missions are designed to facilitate market entry\, strengthen partnerships\, and enhance visibility in two of the world’s most advanced semiconductor markets. \nEU Business Hub @ Semicon Japan 2025\nDates: 15–19 December 2025Location: Tokyo\, JapanDetails & Application: Visit the mission page \nEU Business Hub – Semiconductors Korea 2026\nDates: 9–13 March 2026Location: Seoul\, Republic of KoreaDetails & Application: Visit the mission page \nThese missions target European SMEs and start-ups involved in the semiconductor value chain\, including design\, materials\, equipment\, testing\, packaging\, and related technologies. \nWhat Selected Participants Will Receive?\n\n\nFree exhibition space at two major international trade fairs: Semicon Japan and SEMICON Korea \n\n\nTailored B2B matchmaking with Japanese and Korean companies \n\n\nBusiness support services\, including pre-departure briefings and on-site assistance \n\n\nAccess to networking events and targeted market insights \n\n\nAccommodation covered for four nights during the mission \n\n\nPlease note: Travel costs are the responsibility of participating companies. \nApplication Deadline:\n12 September 2025Early applications are encouraged due to limited places and high interest. \nContact\nFor further information\, promotional materials\, or application support\, please contact us via the EU Business Hub website: https://eubusinesshub.eu \nWe welcome your participation and look forward to supporting your company’s international growth in the semiconductor sector. \nPhoto credit: Semi Japan
URL:https://czechsemiconductorcentre.cz/event/join-the-eu-business-hub-missions-to-japan-korea-deadline-12-september/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/Snimek-obrazovky-2025-07-24-143146.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250903
DTEND;VALUE=DATE:20250905
DTSTAMP:20260923T211052
CREATED:20250710T132410Z
LAST-MODIFIED:20250710T132410Z
UID:1542-1756857600-1757030399@czechsemiconductorcentre.cz
SUMMARY:INSIDE Connect 2025
DESCRIPTION:INSIDE Connect 2025 is an exclusive\, members-only event organised by INSIDE Industry Association. It brings together the full spectrum of Europe’s Electronic Components and Systems (ECS) community\, from researchers and innovators to strategic policymakers with the shared goal of advancing digital innovation across Europe. \nHosted at the Hotel Barceló Málaga\, the event offers a dedicated forum for strategic discussions\, collaborative planning\, and shaping the future direction of Europe’s digital and semiconductor landscape. \nHighlights of the Programme:\n\n\nStrategic outlook on the next EU Multiannual Financial Framework and its impact on digital innovation priorities. \n\n\nIn-depth discussions on key technological trends and challenges\, including AI\, edge computing\, and the evolution of semiconductor technologies. \n\n\nInteractive workshops and roadmapping sessions to translate ideas into practical actions. \n\n\nProject showcases featuring results\, achievements\, and future opportunities. \n\n\nA dynamic space for networking\, knowledge sharing\, and forming new partnerships. \n\n\nNote: Participation is limited to INSIDE members.
URL:https://czechsemiconductorcentre.cz/event/inside-connect-2025/
LOCATION:Malaga\, Spain\, Malaga\, Spain
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/OIaYqWHS05Nh.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250810
DTEND;VALUE=DATE:20250811
DTSTAMP:20260923T211052
CREATED:20250715T110631Z
LAST-MODIFIED:20250715T110631Z
UID:1546-1754784000-1754870399@czechsemiconductorcentre.cz
SUMMARY:ChipStart EU Incubator
DESCRIPTION:Applications are now open for ChipStart EU\, a groundbreaking incubator programme designed to support and accelerate early-stage semiconductor startups across Europe. \nPowered by Silicon Catalyst EU\, and backed by the Chips Joint Undertaking and Malta Enterprise\, this one-year programme offers free\, no-equity incubation to 10 selected startups from EU member states with active Chips JU Competence Centres. \nWhy Apply?\nStartups will gain: \n\n\nAccess to Silicon Catalyst’s global ecosystem\, including EDA tools\, design IP\, and advanced foundry tapeouts \n\n\nA paid mentor from a network of 400+ experienced semiconductor executives \n\n\nTailored virtual training focused on scaling globally competitive chip companies \n\n\nThe support structure of a programme that has helped UK startups raise over €40 million in funding \n\n\nWhether you’re an early-stage startup or a research team yet to incorporate\, ChipStart EU is built to accelerate your journey from idea to impact. \n🗓 Deadline to Apply: August 10\, 2025🔗 Apply now at: https://www.siliconcatalyst.eu/apply \nHave questions? Contact us at chipstarteu@siliconcatalyst.com
URL:https://czechsemiconductorcentre.cz/event/chipstart-eu-incubator/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/07/SiC.UK_ChipStartEU_Logo_v2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250625
DTEND;VALUE=DATE:20250628
DTSTAMP:20260923T211052
CREATED:20250424T072926Z
LAST-MODIFIED:20250425T071118Z
UID:1086-1750809600-1751068799@czechsemiconductorcentre.cz
SUMMARY:Heterogenous Integration: Bolstering Europe’s Resilience
DESCRIPTION:Themed Heterogenous Integration: Bolstering Europe’s Resilience the 3D & Systems Summit 2025 will primarily focus on exploring strategies for enhancing Europe’s semiconductor industry addressing topics as geopolitical dynamics\, market trends\, as well as the latest advancements in chiplet applications and hybrid bonding techniques. The Summit will feature an exclusive exhibition area\, showcasing industry leaders alongside innovative emerging companies. This Summit is a platform for gathering and exchange of knowledge and fostering of collaborations within the semiconductor sector. \nAttendees will have several opportunities for B2B matching\, including networking receptions\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise along the beautiful Elbe River.
URL:https://czechsemiconductorcentre.cz/event/test-event-from-calendar/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/LEB_3195.jpg.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250618
DTEND;VALUE=DATE:20250619
DTSTAMP:20260923T211052
CREATED:20250529T131103Z
LAST-MODIFIED:20250529T131132Z
UID:1460-1750204800-1750291199@czechsemiconductorcentre.cz
SUMMARY:The FAMES Pilot Line Academy
DESCRIPTION:Following the successful launch of the FAMES Pilot Line Open-Access\,\nwe are pleased to invite you to the first edition of the FAMES Academy. \n• Date: June 18\, 2025\n• Location: CEA-Leti Innovation Days–LID World Summit\, Grenoble\, France \nThe FAMES Academy is designed to support startups\, fabless companies\, research institutions and industry stakeholders in making the most of the FAMES Pilot Line. Participants will explore advanced technologies such as FD-SOI\, embedded non-volatile memories\, 3D integration\, RF components\, and DC-DC power management. \nThis hands-on event will feature expert talks\, two panel sessions\, and guidance on how to access the FAMES platform and its state-of-the-art R&D infrastructure. \nWe would be delighted to welcome you to this first FAMES Academy\, where you will gain key insights to accelerate your innovation projects.
URL:https://czechsemiconductorcentre.cz/event/the-fames-pilot-line-academy/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/HEADER_LID25-FAMES_600x350_1748003808.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250617
DTEND;VALUE=DATE:20250620
DTSTAMP:20260923T211052
CREATED:20250509T104751Z
LAST-MODIFIED:20250509T104751Z
UID:1341-1750118400-1750377599@czechsemiconductorcentre.cz
SUMMARY:CEA-Leti Innovation Days
DESCRIPTION:CEA-Leti Innovation Days is back for a new edition! \nLeti Innovation Days 2025\, from June 17 to 19\, will offer you a front-row seat to our most recent advances. Join more than 1\,100 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate! \nMore at: https://leti-innovation-days.com/2025/lid-world/ 
URL:https://czechsemiconductorcentre.cz/event/cea-leti-innovation-days/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/PPT_LID-World25_1920x1080-1024x576-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250617
DTEND;VALUE=DATE:20250618
DTSTAMP:20260923T211052
CREATED:20250509T105458Z
LAST-MODIFIED:20250509T105458Z
UID:1351-1750118400-1750204799@czechsemiconductorcentre.cz
SUMMARY:Silicon Saxony Day
DESCRIPTION:19th Silicon Saxony Day…\n\n\n\n\n\noffers unique insight into future technologies and business solutions covering hardware\, software and connectivity topics.\ngives you the chance to get in touch with like-minded leaders\, engineers\, scientists and business developers and join the hightech community.\nprovides an innovative and international platform for sharing ideas and trends for future information and communications technologies.\n\n\n  \nSilicon Saxony Day is one of the most important international high-tech and networking events in Europe. It offers cross-industry insights into technologies and solutions in the areas of hardware\, software and connectivity. In addition to knowledge and technology transfer\, the goal of this networking event is the open exchange between developers\, producers and users of information and communication technologies (ICT). \nA main stage and several theme islands create space for networking\, professional exchange and exciting insights into players and technologies in the ICT industry. While the main stage with its high-caliber keynotes and panel discussions reflects the entire spectrum of our network\, the theme islands represent a clear technological focus. In short pitches and talks\, the islands offer insights into challenges\, use cases\, lessons learned\, best practices and novel business models. And all this in the Silent Disco concept. \nYou can also look forward to a dedicated B2B matchmaking\, designed to connect you with the right partners for fruitful collaborations. \nCheck website: https://www.silicon-saxony-day.de/ 
URL:https://czechsemiconductorcentre.cz/event/silicon-saxony-day/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/Snimek-obrazovky-2025-05-09-125140.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250616
DTEND;VALUE=DATE:20250628
DTSTAMP:20260923T211052
CREATED:20250520T143150Z
LAST-MODIFIED:20250520T143307Z
UID:1437-1750032000-1751068799@czechsemiconductorcentre.cz
SUMMARY:Summer School on Silicon photonics design and analysis
DESCRIPTION:2-week on-site summer school focused on photonics: The lectures are led by prof. San-Liang Lee (NTUST)\, prof. Ming-Wei Lin (TSRI\, NARL) and Ching-Wei Peng. Practical exercises will take place in the Cadence computer laboratory at the Faculty of Electrical Engineering of the Czech Technical University in Prague. The course will allow students to gain practical experience in the design of photonic components and their application in photonic systems. Students will learn about RSoft\, OptSim\, L-edit photonics\, OptoCompiler\, advanced-design system\, matlab and klayout. They will design specific components and structures in hands-on exercises in the computer lab.\n\nThis course gives a unique opportunity to explore new design techniques for photonics devices and learn about design software used to design photonics chips. The course is free of charge. Course plan can be found here. Application form is here.
URL:https://czechsemiconductorcentre.cz/event/summer-school-on-silicon-photonics-design-and-analysis/
LOCATION:FEE CTU\, Technicka 1902/2\, Prague\, 166 27\, Czech Republic
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/shutterstock_2557861039-scaled.jpg
ORGANIZER;CN="FEE CTU":MAILTO:xprajzlv@fel.cvut.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250608
DTEND;VALUE=DATE:20250609
DTSTAMP:20260923T211052
CREATED:20250529T130559Z
LAST-MODIFIED:20250529T130559Z
UID:1457-1749340800-1749427199@czechsemiconductorcentre.cz
SUMMARY:2025 Chipathon SSCS PICO
DESCRIPTION:The IEEE Solid-State Circuits Society is pleased to announce its fifth open-source integrated circuit (IC) design contest under the umbrella of its PICO (Platform for IC Design Outreach) program. While this contest is open to anyone (no restrictions)\, we encourage the participation of pre-college students\, undergraduates\, and geographical regions that are underrepresented within the IC design community. \nThe goal of this year’s event is to foster collaboration and the development of building blocks that will be ported to the open-source GF180MCU PDK across different design areas. Attendees will be organized into teams\, each led by IC design experts who will share their knowledge and guide participants through the key steps of the design flow to strengthen our community’s design expertise. \n\nCreating MOSbius-style chips in GF180MCU\nDigital Building Blocks with an LLM-driven Workflow\nAI/LLM enhanced Analog Automation using gLayout\n\n\nContest Outline\n\n\nInterested individuals sign up using this form by June 8\, 2025.\nPhase 1 (~June): Participants will explore circuit design and layout in weekly meetings and training sessions. The first weeks will introduce the projects and expectations\, leading to team formation by the end of this phase.\nPhase 2 (~July): Mentors will guide participants on tool installation\, design flows for building blocks\, and design methodologies with examples to meet circuit specifications.\nPhase 3 (~August): Design reviews will be scheduled for participants (per team) to present their progress and receive feedback.\nPhase 4 (~September): All designs will undergo circuit verification and validation with a clean DRC and LVS database by the GF180MCU tape-out deadline.\nPhase 5 (4 – 5 months after TO): Each team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators.\n\n\nContest Design Areas\n\nEach team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators. \n\nCreating MOSbius-style Chips in GF180MCU\n\nThe current MOSbius architecture and chip implementation support transistor-level experimentation on breadboards using IC-style circuit topologies. The chip allows learners to bridge the gap between theory and simulation vs. lab measurements before they engage in their own full-custom chip design. \nThe design of the MOSbius chip itself is very challenging given it combines (analog) transistor cells with an on-chip digitally programmable switch fabric. The verification complexity of highly programmable chips like the MOSbius grows very quickly. The design further needs to be robust against ESD and possible misuse. \nDesigns can start from the current architecture (using 65nm thick-oxide transistors)\, but teams are encouraged to explore their own custom transistor-cell designs and switch fabrics. A key requirement is that the chips\, besides passive components\, should only need minimal external components (e.g.\, be programmable from a low-cost microcontroller) to build experiments. \nA key outcome will be the opportunity to use the fabricated chips to set up labs to train new IC designers across the world. Extra consideration will be given to teams that incorporate exciting experiments using their chip for educational labs. \n\nDigital Building Blocks with an LLM-driven Workflow\n\nWe propose to design several building blocks – such as small cores\, a new set of standard cells and logic families (only library is available here)\, new memory blocks (like SRAM\, eDRAM or other topologies). In parallel\, the project will explore developing an LLM-driven digital design flow that can autonomously or semi-autonomously generate complete digital systems from natural language instructions. The goal is to demonstrate how generative AI can speed up digital design workflows\, from specification to GDSII\, by enabling intelligent interpretation\, decision-making\, and feedback at every stage. Our long-term vision is to pave the way for scalable\, natural language–driven hardware development through a verifiable reward system. \n\nAI/LLM Enhanced Analog Automation Using gLayout\n\nChipalooza was the first Efabless open-source analog and mixed-signal design challenge event. Its goal was to create a library of different devices that could be reused by other IC designers for education\, reference\, and enhancement. The IP blocks in the Chipalooza challenge include ADCs\, DACs\, opamps\, filters\, temperature sensors\, bandgaps\, power-on reset\, brown-out detector\, crystal oscillators\, and PLLs. \nFor the 2025 contest\, teams are asked to port one of these IPs from SKY130 to GF180MCU using the GLayout layout automation framework. This framework enables the use of large language models (LLM) to translate natural language instructions into executable commands for the layout process. GLayout was the core of the 2024 SSCS “PICO” open-source chipathon\, allowing it to generate DRC and LVS valid layouts for different projects. \n\nIntegration of the Different Designs and Padring\n\nThe template provided for the Chipathon 2023 will be used to integrate all the designs. Check out this presentation for more details about the template. Also\, here is the link to the integrated projects from the 2023 Chipathon. \nReach out to Mehdi Saligane (mehdi_saligane@brown.edu) with any questions.
URL:https://czechsemiconductorcentre.cz/event/2025-chipathon-sscs-pico/
CATEGORIES:External Event
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20250603
DTEND;VALUE=DATE:20250607
DTSTAMP:20260923T211052
CREATED:20250506T131618Z
LAST-MODIFIED:20250506T131618Z
UID:1336-1748908800-1749254399@czechsemiconductorcentre.cz
SUMMARY:EPoSS Annual Forum 2025
DESCRIPTION:Accelerating Innovations in Smart Systems. Empowering Competitive European Solutions. This is the motto for the 2025 edition of the EPoSS Annual Forum. It will take place from June 03-06 in Neuchâtel\, Switzerland. \nJoin the leading annual gathering of the European Smart Systems Community that will be kindly hosted by our EPoSS member CSEM.
URL:https://czechsemiconductorcentre.cz/event/eposs-annual-forum-2025/
LOCATION:Rue de la Maladière 71b 2000 Neuchâtel Switzerland\, Rue de la Maladière 71b\, Neuchâtel\, 2000\, Switzerland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/EPoSS-AF-Header-Sponsors_20250417.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20250513
DTEND;VALUE=DATE:20250515
DTSTAMP:20260923T211052
CREATED:20250424T105530Z
LAST-MODIFIED:20250425T065846Z
UID:1112-1747094400-1747267199@czechsemiconductorcentre.cz
SUMMARY:Czech Semicon Days 2025
DESCRIPTION:In May\, the CzechInvest Agency organises a series of events under the name Czech Semicon Days\, whose common theme is the development of the semiconductor industry. This year\, the industry in the Czech Republic is celebrating 70 years from its first technological milestones to its current ambition to become a major player in the European and global chip ecosystem.  \n“The Czech Republic is in an excellent position to become a global player in the chip industry\, we have a strong industrial tradition and functional supply chains. We offer quality technical education\, a number of innovative companies and universities that are open to cooperation with business on research and development projects. Czech Semicon Days are an opportunity to show partners and foreign investors that we are ready to fully exploit this potential\,” said Jan Michal\, Director General of the CzechInvest agency. \nCzech Semicon Days will take place in Prague on 13 and 14 May 2025 and will offer a number of specialised events. The programme will be launched by the second edition of the Czech Investment Forum on 13 May in the Fanta Building. It will be a full-day conference where speakers will present the Czech semiconductor ecosystem and the new National Semiconductor Strategy. Expert panel discussions will focus on current geopolitical challenges or opportunities for the Czech Republic’s involvement in global supply chains. Speakers will include a number of prominent Czech and international chip experts\, including Prof. Konrad Young\, former vice president of Taiwanese chip giant TSMC\, Michal Lorenc\, vice president of the Czech National Semiconductor Cluster\, and Karel Masařík\, director of the newly established Czech Semiconductor Centre. \nThe second day will be dedicated to seminars\, round tables\, workshops and networking. Czech-Taiwanese Semiconductors supplier day will focus on strengthening economic cooperation between Taiwanese and Czech partners\, as well as building and strengthening supply chains. Discussions will focus on linking the semiconductor industry with other backbone sectors of the Czech economy. Participants will have the opportunity to discuss opportunities for Czech-Taiwanese cooperation with Prof. Konrad Young or approaches to building the necessary expertise with representatives of ITRI (Industrial Technology Research Institute). Another event on 14 May is the Czech Semiconductor Ecosystem Day\, which is an opportunity to share examples of good practice for regional development\, in cooperation between universities\, local governments\, chambers of commerce and other entities\, and to gain inspiration from foreign regions that already have rich experience in this area. \nAlso on 14 May 2025\, the Czech Semicon Workshop will be held\, targeting international semiconductor companies\, investors\, who will be introduced to the Czech investment business environment\, opportunities for financing their investments and visa acceleration programmes for foreign professionals. The main partner of Czech Semicon Days is the Association for Foreign Investment. The Czech National Semiconductor Cluster and the Supply Chain Resilience Center are specialised partners. \n 
URL:https://czechsemiconductorcentre.cz/event/this-is-the-fourth-test-calendar-event/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/1744719655_1.png
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