BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Czech Semiconductor Centre - ECPv6.15.18//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Czech Semiconductor Centre
X-ORIGINAL-URL:https://czechsemiconductorcentre.cz
X-WR-CALDESC:Events for Czech Semiconductor Centre
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:Europe/Prague
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20240331T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20241027T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20250330T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20251026T010000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
DTSTART:20260329T010000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
DTSTART:20261025T010000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250618
DTEND;VALUE=DATE:20250619
DTSTAMP:20260924T001214
CREATED:20250529T131103Z
LAST-MODIFIED:20250529T131132Z
UID:1460-1750204800-1750291199@czechsemiconductorcentre.cz
SUMMARY:The FAMES Pilot Line Academy
DESCRIPTION:Following the successful launch of the FAMES Pilot Line Open-Access\,\nwe are pleased to invite you to the first edition of the FAMES Academy. \n• Date: June 18\, 2025\n• Location: CEA-Leti Innovation Days–LID World Summit\, Grenoble\, France \nThe FAMES Academy is designed to support startups\, fabless companies\, research institutions and industry stakeholders in making the most of the FAMES Pilot Line. Participants will explore advanced technologies such as FD-SOI\, embedded non-volatile memories\, 3D integration\, RF components\, and DC-DC power management. \nThis hands-on event will feature expert talks\, two panel sessions\, and guidance on how to access the FAMES platform and its state-of-the-art R&D infrastructure. \nWe would be delighted to welcome you to this first FAMES Academy\, where you will gain key insights to accelerate your innovation projects.
URL:https://czechsemiconductorcentre.cz/event/the-fames-pilot-line-academy/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/HEADER_LID25-FAMES_600x350_1748003808.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250617
DTEND;VALUE=DATE:20250620
DTSTAMP:20260924T001214
CREATED:20250509T104751Z
LAST-MODIFIED:20250509T104751Z
UID:1341-1750118400-1750377599@czechsemiconductorcentre.cz
SUMMARY:CEA-Leti Innovation Days
DESCRIPTION:CEA-Leti Innovation Days is back for a new edition! \nLeti Innovation Days 2025\, from June 17 to 19\, will offer you a front-row seat to our most recent advances. Join more than 1\,100 semiconductor industry professionals at this three-day global event and come away equipped and inspired to innovate! \nMore at: https://leti-innovation-days.com/2025/lid-world/ 
URL:https://czechsemiconductorcentre.cz/event/cea-leti-innovation-days/
LOCATION:Grenoble\, Grenoble\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/PPT_LID-World25_1920x1080-1024x576-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250617
DTEND;VALUE=DATE:20250618
DTSTAMP:20260924T001214
CREATED:20250509T105458Z
LAST-MODIFIED:20250509T105458Z
UID:1351-1750118400-1750204799@czechsemiconductorcentre.cz
SUMMARY:Silicon Saxony Day
DESCRIPTION:19th Silicon Saxony Day…\n\n\n\n\n\noffers unique insight into future technologies and business solutions covering hardware\, software and connectivity topics.\ngives you the chance to get in touch with like-minded leaders\, engineers\, scientists and business developers and join the hightech community.\nprovides an innovative and international platform for sharing ideas and trends for future information and communications technologies.\n\n\n  \nSilicon Saxony Day is one of the most important international high-tech and networking events in Europe. It offers cross-industry insights into technologies and solutions in the areas of hardware\, software and connectivity. In addition to knowledge and technology transfer\, the goal of this networking event is the open exchange between developers\, producers and users of information and communication technologies (ICT). \nA main stage and several theme islands create space for networking\, professional exchange and exciting insights into players and technologies in the ICT industry. While the main stage with its high-caliber keynotes and panel discussions reflects the entire spectrum of our network\, the theme islands represent a clear technological focus. In short pitches and talks\, the islands offer insights into challenges\, use cases\, lessons learned\, best practices and novel business models. And all this in the Silent Disco concept. \nYou can also look forward to a dedicated B2B matchmaking\, designed to connect you with the right partners for fruitful collaborations. \nCheck website: https://www.silicon-saxony-day.de/ 
URL:https://czechsemiconductorcentre.cz/event/silicon-saxony-day/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/Snimek-obrazovky-2025-05-09-125140.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250616
DTEND;VALUE=DATE:20250628
DTSTAMP:20260924T001214
CREATED:20250520T143150Z
LAST-MODIFIED:20250520T143307Z
UID:1437-1750032000-1751068799@czechsemiconductorcentre.cz
SUMMARY:Summer School on Silicon photonics design and analysis
DESCRIPTION:2-week on-site summer school focused on photonics: The lectures are led by prof. San-Liang Lee (NTUST)\, prof. Ming-Wei Lin (TSRI\, NARL) and Ching-Wei Peng. Practical exercises will take place in the Cadence computer laboratory at the Faculty of Electrical Engineering of the Czech Technical University in Prague. The course will allow students to gain practical experience in the design of photonic components and their application in photonic systems. Students will learn about RSoft\, OptSim\, L-edit photonics\, OptoCompiler\, advanced-design system\, matlab and klayout. They will design specific components and structures in hands-on exercises in the computer lab.\n\nThis course gives a unique opportunity to explore new design techniques for photonics devices and learn about design software used to design photonics chips. The course is free of charge. Course plan can be found here. Application form is here.
URL:https://czechsemiconductorcentre.cz/event/summer-school-on-silicon-photonics-design-and-analysis/
LOCATION:FEE CTU\, Technicka 1902/2\, Prague\, 166 27\, Czech Republic
CATEGORIES:Organized by CSC
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/shutterstock_2557861039-scaled.jpg
ORGANIZER;CN="FEE CTU":MAILTO:xprajzlv@fel.cvut.cz
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250608
DTEND;VALUE=DATE:20250609
DTSTAMP:20260924T001214
CREATED:20250529T130559Z
LAST-MODIFIED:20250529T130559Z
UID:1457-1749340800-1749427199@czechsemiconductorcentre.cz
SUMMARY:2025 Chipathon SSCS PICO
DESCRIPTION:The IEEE Solid-State Circuits Society is pleased to announce its fifth open-source integrated circuit (IC) design contest under the umbrella of its PICO (Platform for IC Design Outreach) program. While this contest is open to anyone (no restrictions)\, we encourage the participation of pre-college students\, undergraduates\, and geographical regions that are underrepresented within the IC design community. \nThe goal of this year’s event is to foster collaboration and the development of building blocks that will be ported to the open-source GF180MCU PDK across different design areas. Attendees will be organized into teams\, each led by IC design experts who will share their knowledge and guide participants through the key steps of the design flow to strengthen our community’s design expertise. \n\nCreating MOSbius-style chips in GF180MCU\nDigital Building Blocks with an LLM-driven Workflow\nAI/LLM enhanced Analog Automation using gLayout\n\n\nContest Outline\n\n\nInterested individuals sign up using this form by June 8\, 2025.\nPhase 1 (~June): Participants will explore circuit design and layout in weekly meetings and training sessions. The first weeks will introduce the projects and expectations\, leading to team formation by the end of this phase.\nPhase 2 (~July): Mentors will guide participants on tool installation\, design flows for building blocks\, and design methodologies with examples to meet circuit specifications.\nPhase 3 (~August): Design reviews will be scheduled for participants (per team) to present their progress and receive feedback.\nPhase 4 (~September): All designs will undergo circuit verification and validation with a clean DRC and LVS database by the GF180MCU tape-out deadline.\nPhase 5 (4 – 5 months after TO): Each team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators.\n\n\nContest Design Areas\n\nEach team of participants and volunteers with access to lab facilities will test the designs with lab measurements. The measurement data obtained will be added to the repositories containing the layout generators. \n\nCreating MOSbius-style Chips in GF180MCU\n\nThe current MOSbius architecture and chip implementation support transistor-level experimentation on breadboards using IC-style circuit topologies. The chip allows learners to bridge the gap between theory and simulation vs. lab measurements before they engage in their own full-custom chip design. \nThe design of the MOSbius chip itself is very challenging given it combines (analog) transistor cells with an on-chip digitally programmable switch fabric. The verification complexity of highly programmable chips like the MOSbius grows very quickly. The design further needs to be robust against ESD and possible misuse. \nDesigns can start from the current architecture (using 65nm thick-oxide transistors)\, but teams are encouraged to explore their own custom transistor-cell designs and switch fabrics. A key requirement is that the chips\, besides passive components\, should only need minimal external components (e.g.\, be programmable from a low-cost microcontroller) to build experiments. \nA key outcome will be the opportunity to use the fabricated chips to set up labs to train new IC designers across the world. Extra consideration will be given to teams that incorporate exciting experiments using their chip for educational labs. \n\nDigital Building Blocks with an LLM-driven Workflow\n\nWe propose to design several building blocks – such as small cores\, a new set of standard cells and logic families (only library is available here)\, new memory blocks (like SRAM\, eDRAM or other topologies). In parallel\, the project will explore developing an LLM-driven digital design flow that can autonomously or semi-autonomously generate complete digital systems from natural language instructions. The goal is to demonstrate how generative AI can speed up digital design workflows\, from specification to GDSII\, by enabling intelligent interpretation\, decision-making\, and feedback at every stage. Our long-term vision is to pave the way for scalable\, natural language–driven hardware development through a verifiable reward system. \n\nAI/LLM Enhanced Analog Automation Using gLayout\n\nChipalooza was the first Efabless open-source analog and mixed-signal design challenge event. Its goal was to create a library of different devices that could be reused by other IC designers for education\, reference\, and enhancement. The IP blocks in the Chipalooza challenge include ADCs\, DACs\, opamps\, filters\, temperature sensors\, bandgaps\, power-on reset\, brown-out detector\, crystal oscillators\, and PLLs. \nFor the 2025 contest\, teams are asked to port one of these IPs from SKY130 to GF180MCU using the GLayout layout automation framework. This framework enables the use of large language models (LLM) to translate natural language instructions into executable commands for the layout process. GLayout was the core of the 2024 SSCS “PICO” open-source chipathon\, allowing it to generate DRC and LVS valid layouts for different projects. \n\nIntegration of the Different Designs and Padring\n\nThe template provided for the Chipathon 2023 will be used to integrate all the designs. Check out this presentation for more details about the template. Also\, here is the link to the integrated projects from the 2023 Chipathon. \nReach out to Mehdi Saligane (mehdi_saligane@brown.edu) with any questions.
URL:https://czechsemiconductorcentre.cz/event/2025-chipathon-sscs-pico/
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/GrfN7G6XEAA-QHS.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250603
DTEND;VALUE=DATE:20250607
DTSTAMP:20260924T001214
CREATED:20250506T131618Z
LAST-MODIFIED:20250506T131618Z
UID:1336-1748908800-1749254399@czechsemiconductorcentre.cz
SUMMARY:EPoSS Annual Forum 2025
DESCRIPTION:Accelerating Innovations in Smart Systems. Empowering Competitive European Solutions. This is the motto for the 2025 edition of the EPoSS Annual Forum. It will take place from June 03-06 in Neuchâtel\, Switzerland. \nJoin the leading annual gathering of the European Smart Systems Community that will be kindly hosted by our EPoSS member CSEM.
URL:https://czechsemiconductorcentre.cz/event/eposs-annual-forum-2025/
LOCATION:Rue de la Maladière 71b 2000 Neuchâtel Switzerland\, Rue de la Maladière 71b\, Neuchâtel\, 2000\, Switzerland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/EPoSS-AF-Header-Sponsors_20250417.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250513
DTEND;VALUE=DATE:20250515
DTSTAMP:20260924T001214
CREATED:20250424T105530Z
LAST-MODIFIED:20250425T065846Z
UID:1112-1747094400-1747267199@czechsemiconductorcentre.cz
SUMMARY:Czech Semicon Days 2025
DESCRIPTION:In May\, the CzechInvest Agency organises a series of events under the name Czech Semicon Days\, whose common theme is the development of the semiconductor industry. This year\, the industry in the Czech Republic is celebrating 70 years from its first technological milestones to its current ambition to become a major player in the European and global chip ecosystem.  \n“The Czech Republic is in an excellent position to become a global player in the chip industry\, we have a strong industrial tradition and functional supply chains. We offer quality technical education\, a number of innovative companies and universities that are open to cooperation with business on research and development projects. Czech Semicon Days are an opportunity to show partners and foreign investors that we are ready to fully exploit this potential\,” said Jan Michal\, Director General of the CzechInvest agency. \nCzech Semicon Days will take place in Prague on 13 and 14 May 2025 and will offer a number of specialised events. The programme will be launched by the second edition of the Czech Investment Forum on 13 May in the Fanta Building. It will be a full-day conference where speakers will present the Czech semiconductor ecosystem and the new National Semiconductor Strategy. Expert panel discussions will focus on current geopolitical challenges or opportunities for the Czech Republic’s involvement in global supply chains. Speakers will include a number of prominent Czech and international chip experts\, including Prof. Konrad Young\, former vice president of Taiwanese chip giant TSMC\, Michal Lorenc\, vice president of the Czech National Semiconductor Cluster\, and Karel Masařík\, director of the newly established Czech Semiconductor Centre. \nThe second day will be dedicated to seminars\, round tables\, workshops and networking. Czech-Taiwanese Semiconductors supplier day will focus on strengthening economic cooperation between Taiwanese and Czech partners\, as well as building and strengthening supply chains. Discussions will focus on linking the semiconductor industry with other backbone sectors of the Czech economy. Participants will have the opportunity to discuss opportunities for Czech-Taiwanese cooperation with Prof. Konrad Young or approaches to building the necessary expertise with representatives of ITRI (Industrial Technology Research Institute). Another event on 14 May is the Czech Semiconductor Ecosystem Day\, which is an opportunity to share examples of good practice for regional development\, in cooperation between universities\, local governments\, chambers of commerce and other entities\, and to gain inspiration from foreign regions that already have rich experience in this area. \nAlso on 14 May 2025\, the Czech Semicon Workshop will be held\, targeting international semiconductor companies\, investors\, who will be introduced to the Czech investment business environment\, opportunities for financing their investments and visa acceleration programmes for foreign professionals. The main partner of Czech Semicon Days is the Association for Foreign Investment. The Czech National Semiconductor Cluster and the Supply Chain Resilience Center are specialised partners. \n 
URL:https://czechsemiconductorcentre.cz/event/this-is-the-fourth-test-calendar-event/
LOCATION:Prague\, Prague\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/1744719655_1.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250512
DTEND;VALUE=DATE:20250516
DTSTAMP:20260924T001214
CREATED:20250509T105051Z
LAST-MODIFIED:20250509T105051Z
UID:1346-1747008000-1747353599@czechsemiconductorcentre.cz
SUMMARY:RISC-V Summit Europe
DESCRIPTION:The RISC-V Summit Europe is the premier event that connects the European movers and shakers – from industry\, government\, research\, academia and ecosystem support – that are building the future of innovation on RISC-V. \nRISC-V\, the open standard instruction set architecture (ISA)\, is enabling a range of new applications and research that will define the future of computing in Europe. The region has been central to RISC-V’s success\, with one-third of RISC-V’s global community based in Europe. \nRISC-V Summit Europe takes place in Paris from Monday 12th to Thursday 15th May\, 2025. The combination of strong industrial and academic communities is key to the success of RISC-V in Europe\, and for this reason the conference is designed to help attendees to explore both commercial and research applications. RISC-V Summit Europe is an opportunity not to be missed. Come to Paris to be part of the new wave of European computing innovation!
URL:https://czechsemiconductorcentre.cz/event/risc-v-summit-europe/
LOCATION:Paris\, Paris\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/05/Snimek-obrazovky-2025-05-09-124941.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250512
DTEND;VALUE=DATE:20250514
DTSTAMP:20260924T001214
CREATED:20250424T135934Z
LAST-MODIFIED:20250425T070608Z
UID:1137-1747008000-1747180799@czechsemiconductorcentre.cz
SUMMARY:Key Emerging Technologies for Future Industrial Applications
DESCRIPTION:This Workshop will focus on strengthening international cooperation in the area of advanced computing and advanced functionalities\, taking into account the heterogeneous integration and the sustainability of these technologies\, in order to reinforce the resilience of the European semiconductor ecosystem and value chain by: \n– Gathering new information on the recent evolution of the international environment of the semiconductor industry \n– Identifying and discussing critical needs for future semiconductor technologies \n– Obtaining a prioritized list of technologies that should be supported as key competences in the European Union \n– Specifying the strengths and weaknesses of leading semiconductor countries in the semiconductor value chain \n– Identifying the most urgent challenges where cooperation with other countries should be initiated or developed \n– Proposing recommendations for international research cooperation on emerging semiconductor technologies \n– Highlighting the need of new standards for innovative semiconductor technologies \nThe programme is available here.
URL:https://czechsemiconductorcentre.cz/event/fifth-past-event-test/
LOCATION:Warsaw\, Poland\, Warsaw\, Poland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/Firefly-semiconductor-chips-and-circuits-736014.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20250512
DTEND;VALUE=DATE:20250516
DTSTAMP:20260924T001214
CREATED:20250424T105455Z
LAST-MODIFIED:20250425T070833Z
UID:1110-1747008000-1747353599@czechsemiconductorcentre.cz
SUMMARY:IEEE International Conference on Industrial Cyber-Physical Systems
DESCRIPTION:Continuing with the success of the past ICPS-Editions held in Russia (2018)\, Taiwan (2019)\, Finland (2020)\, Canada (2021)\, the UK (2022)\, China (2023)\, and the USA (2024)\, ICPS 2025\, under the motto “The Ongoing Digital Transformation”\, aims to provide an international platform for cutting-edge research and professional interactions for the development of ICPS. Track information and submission deadlines for papers\, tutorials\, and special sessions are available on the conference website. Stay up to date via the ICPS LinkedIn page.
URL:https://czechsemiconductorcentre.cz/event/third-test-calendar-event/
LOCATION:Emden\, Germany\, Emden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/Snimek-obrazovky-2025-04-18-115947.png
END:VEVENT
END:VCALENDAR