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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260603
DTEND;VALUE=DATE:20260604
DTSTAMP:20260923T145112
CREATED:20260408T074732Z
LAST-MODIFIED:20260408T074732Z
UID:2188-1780444800-1780531199@czechsemiconductorcentre.cz
SUMMARY:SEMI Europe Policy Forum 2026
DESCRIPTION:Join leading policymakers\, industry executives and technology experts at the SEMI Europe Policy Forum 2026\, a high-level gathering dedicated to shaping the future of Europe’s semiconductor ecosystem. \nIn an era defined by rapid geopolitical shifts and technological transformation\, Europe faces both unprecedented challenges and unique opportunities. This year’s forum will explore how Europe can strengthen its strategic position\, enhance supply chain resilience\, and secure long-term economic competitiveness in the global semiconductor landscape. \n\nWhy Attend?\nThe SEMI Europe Policy Forum brings together key stakeholders from across the semiconductor value chain and public sector to: \n\nExamine the impact of global geopolitical dynamics on Europe’s technology leadership\nDiscuss the next phase of the European Chips Act and its role in securing Europe’s tech future\nAddress sustainability and competitiveness challenges across the industry\nExplore strategies for building a skilled workforce for the future\nFoster international collaboration and strategic partnerships\n\n\nWho Should Attend?\nThis forum is designed for decision-makers and influencers\, including: \n\nEU and national policymakers\, public sector leaders and diplomatic representatives\nSenior executives and industry leaders from semiconductor and technology companies\nR&D professionals\, innovation leaders and supply chain stakeholders\nRepresentatives from academia\, research institutions and think tanks\n\n\nProgramme Highlights\nParticipants can look forward to a full-day programme featuring: \n\nHigh-level keynote sessions and panel discussions\nExpert insights on policy\, innovation and competitiveness\nNetworking opportunities with European and global leaders\nEvening reception and networking dinner\n\nKey topics include Europe’s tech sovereignty\, workforce development\, sustainability challenges\, and global partnerships shaping the future of semiconductors. \n\nBe Part of the Conversation\nAs Europe navigates a rapidly evolving global landscape\, collaboration between industry and policymakers has never been more critical. The SEMI Europe Policy Forum offers a unique platform to exchange ideas\, influence policy direction\, and contribute to a resilient and competitive European semiconductor ecosystem. \n👉 Register now
URL:https://czechsemiconductorcentre.cz/event/semi-europe-policy-forum-2026/
LOCATION:Brussels\, Brussels\, Belgium
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/04/SEPF_360x317px.png.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260605
DTSTAMP:20260923T145112
CREATED:20260520T091830Z
LAST-MODIFIED:20260520T091902Z
UID:2361-1780531200-1780617599@czechsemiconductorcentre.cz
SUMMARY:Forming\, storming\, norming and performing of European Semiconductor startups meetup
DESCRIPTION:EuroCDP and Silicon Catalyst.EU (via Malta Semiconductor Competence Centre) are co‑hosting the EU Semiconductor FSNP Meetup – targeted working day bringing together semiconductor startups\, VCs\, corporates\, and ecosystem leaders. \nWelcome to forming\, storming\, norming and performing of European semiconductor startups. This is a curated afternoon and evening event\, focusing exclusively on semiconductor startups and investors. The beautiful chateau location has been carefully chosen for easy access from Bordeaux station and airport for your same day arrival from anywhere in Europe. You will enjoy high-value conversations without the noise of broader tech events as the sun sets over the vineyards of the most hallowed wine growing soil in the world. \n​We have a packed agenda of investor insights\, funding discussions\, fast-paced startup pitch sessions and a deep insight into the geopolitical semiconductor dynamics challenging Europe’s chip ecosystem. \nDesigned for founders\, VCs\, and ecosystem leaders\, the day aims to spark meaningful connections and knowledge sharing. \nThe day closes by enjoying the finest wines in the world at our Bordeaux wine tasting social event led by one of the region’s top female sommeliers. \n​The event is free and dedicated to startup founders\, investors and ecosystem leaders. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/forming-storming-norming-and-performing-of-european-semiconductor-startups-meetup/
LOCATION:Château de Seguin\, 3 Chem. du Bon Coin\, Lignan-de-Bordeaux\, 33360\, France
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778664931554.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260604
DTEND;VALUE=DATE:20260606
DTSTAMP:20260923T145112
CREATED:20260521T081219Z
LAST-MODIFIED:20260521T081247Z
UID:2373-1780531200-1780703999@czechsemiconductorcentre.cz
SUMMARY:European Semiconductor Collaborations Days
DESCRIPTION:Chips Without Borders will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. \nHungarian SMEs\, industrial stakeholders\, and the HCHiP consortium itself will present their profiles\, ideas\, and international collaboration opportunities. This event also provides an opportunity for CCCs and our other European partners to present themselves\, their profiles\, and the areas in which they are seeking partners through posters and presentations. \nMore informations: https://hchip.hu/en/2026/04/15/european-semiconductor-collaboration-days-2/ \nEuropean Semiconductor Collaboration Day\, taking place on 4–5 June 2026 in Budapest\, Hungary. “Chips Without Borders” will bring together key stakeholders from across the European semiconductor ecosystem\, including industry leaders\, SMEs\, research organizations\, and policy representatives. The program is designed to foster collaboration\, showcase innovation\, and strengthen international partnerships. Venue: Novotel Budapest Danube (Budapest\, Bem rakpart 33-34\, 1027) The participation is free\, but it requires registration. \nRegister here: https://lnkd.in/dB2mS2kG \nFor questions\, please contact us at: hchip@hchip.hu
URL:https://czechsemiconductorcentre.cz/event/european-semiconductor-collaborations-days/
LOCATION:Budapest\, Budapest\, Hungary
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1778062652574-Hchip_European_Semiconductor_Collaboration_Days_cover.webp
ORGANIZER;CN="Hchip":MAILTO:hchip@hchip.hu
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260608
DTEND;VALUE=DATE:20260613
DTSTAMP:20260923T145112
CREATED:20260324T125511Z
LAST-MODIFIED:20260324T125721Z
UID:2162-1780876800-1781308799@czechsemiconductorcentre.cz
SUMMARY:RISC-V Summit Europe
DESCRIPTION:Join us at the RISC-V Summit Europe 2026\, the leading European event dedicated to the open standard RISC-V architecture and its rapidly evolving ecosystem. \nTaking place in Bologna\, Italy\, from 8–12 June 2026\, the summit brings together key stakeholders from industry\, academia\, research\, and government to explore the future of computing and innovation built on RISC-V. \nThe programme will feature: \n\nInspiring keynotes and technical sessions\nPanels\, tutorials\, and workshops\nIndustry exhibitions\, demos\, and poster sessions\nExtensive networking opportunities with leaders across semiconductors\, AI\, embedded systems\, HPC\, and beyond\n\nRISC-V\, as an open and flexible instruction set architecture\, is enabling new applications and research that are shaping the future of computing in Europe and globally. \nThe summit offers a unique platform to exchange knowledge\, showcase innovations\, and strengthen collaboration across the European and global RISC-V community. \n📍 Location: Bologna Congress Center\, Italy📅 Dates: 8–12 June 2026🔗 Learn more and register: RISC-V Summit Europe 2026 website
URL:https://czechsemiconductorcentre.cz/event/risc-v-summit-europe-2/
LOCATION:Bologna\, Bologna\, Italy
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/Snimek-obrazovky-2026-03-24-135153.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260609
DTEND;VALUE=DATE:20260610
DTSTAMP:20260923T145112
CREATED:20260529T122352Z
LAST-MODIFIED:20260529T123149Z
UID:2425-1780963200-1781049599@czechsemiconductorcentre.cz
SUMMARY:Q-LAB Grand Opening
DESCRIPTION:We are pleased to invite you to the official opening of Q-LAB\, a state-of-the-art technical cleanliness laboratory developed by QPAG in cooperation with ZEISS\, taking place on 9 June 2026 at the QPAG Technology Centre in Brno. \nIn today’s manufacturing environment\, even microscopic contaminants can significantly affect product performance\, durability and safety. Q-LAB has been established as a specialised centre for technical cleanliness testing and contamination analysis in accordance with VDA 19.1 / ISO 16232 standards\, operating in an ISO 7 cleanroom environment. \nWhat to Expect\n\nExpert presentations on technical cleanliness and quality assurance\nParticle analysis demonstrations in cooperation with ZEISS\nGuided tours of the QPAG Technology Centre\nLive demonstrations of:\n\nQ-LAB technical cleanliness laboratory (ISO 7)\nAccredited calibration laboratory\nPrecision measurement and 3D scanning technologies\nAutomated quality control solutions\nAI-powered visual inspection systems\n\n\nNetworking opportunities with industry professionals and technology partners\n\nEvent Details\n📅 Date: 9 June 2026📍 Venue: QPAG Technology Centre\, Kaštanová 530/125b\, Brno\, Czech Republic🕘 Morning Session: Registration 08:30 | Opening 09:00 (full)🕐 Afternoon Session: Registration 12:30 | Opening 13:00(Both sessions feature the same programme content.) \nThe event is intended for manufacturing and technical directors\, quality management professionals\, process engineers and specialists from the automotive\, aerospace\, engineering\, medical and high-tech industries. \nFor registration and further information\, please visit:Q-LAB Registration & Event Details \nWe look forward to welcoming you to Q-LAB and sharing the future of technical cleanliness\, advanced inspection and quality assurance. ✨
URL:https://czechsemiconductorcentre.cz/event/q-lab-grand-opening/
LOCATION:Lab Q-LAB\, Kaštanová 125b\, Brno\, Czech Republic
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/ttt-scaled-uai-1032x688-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260609T100000
DTEND;TZID=Europe/Prague:20260609T110000
DTSTAMP:20260923T145112
CREATED:20260604T094550Z
LAST-MODIFIED:20260604T094550Z
UID:2449-1780999200-1781002800@czechsemiconductorcentre.cz
SUMMARY:Technology Offers & Collaboration Pathways with NanoIC Pilot Line and FC3 Chips Competence Center
DESCRIPTION:Join us on June 9 for the second webinar of the aCCCess series dedicated to European Pilot Lines. \nThis session will feature the NanoIC Pilot Line and the FC3 Chips Competence Center\, showcasing cutting-edge capabilities and illustrating how their partnership enables seamless access to expertise\, services\, and innovation support. Don’t miss this opportunity to explore how these synergies accelerate the path from research to industrial application across Europe. It is free of charge. Please register here. \n📍 Programme : \n\n10:00 – 10:05 Introduction – aCCCess project\n\nLaure de Tassigny – European Project Manager\, Minalogic \n\n10:05 – 10:15 NanoIC Introduction and Access model\n\nGiuseppe Fiorentino – Programme Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:15 – 10:25NanoIC Technology offer\n\nNina Bazzazian R&D Project Leader – NanoIC Pilot Line Outreach and Access\, IMEC \n\n10:25 – 10:35 NanoIC Workforce and Training opportunities\n\nRuxandra Marina Florea – R&D Project Manager\, NanoIC Pilot Line – IMEC – IC-Link \n\n10:35 – 10:50 FC3 Chips Competence Center approach to tailored trainings\n\nDavid Maes Research Valorization Manager\, FC3 Chips Competence Center – KU Leuven \n\n10:50 – 11:00 Q&A
URL:https://czechsemiconductorcentre.cz/event/technology-offers-collaboration-pathways-with-nanoic-pilot-line-and-fc3-chips-competence-center/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/1778664216731.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260610T110000
DTEND;TZID=Europe/Prague:20260610T120000
DTSTAMP:20260923T145112
CREATED:20260604T095321Z
LAST-MODIFIED:20260604T095321Z
UID:2453-1781089200-1781092800@czechsemiconductorcentre.cz
SUMMARY:ALL2GaN Insights: Driving Greener Power Electronics
DESCRIPTION:We are pleased to invite you to the next session of the ALL2GaN Insights: Driving Greener Power Electronics – The Wednesday Webinar Series. \nWebinar #5: QuanFINE high-performance substrates for power applications and devicesDate: Wednesday\, 10 June 2026Time: 11:00 a.m.Format: Live online via WebExDuration: 60 minutesParticipation: Public event with open registration \nThe webinar will focus on QuanFINE high-performance substrates for power applications and devices and will feature two speakers closely involved in the ALL2GaN project: \nMichael Salter\, RISE Research Institute of SwedenAnders Lundskog\, SweGaN \nMichael Salter will present the latest results of RISE GaN HEMT device development within the ALL2GaN project\, including E-mode/D-mode devices using SweGaN QuanFINE GaN/SiC epi substrates and vertical nanowire HEMT devices. \nAnders Lundskog will introduce SweGaN and QuanFINE Epitaxy\, followed by an overview of Mg-doping profile tuning. \nThe webinar offers an opportunity to discover recent developments in GaN technology\, learn from European research and industry experts\, and engage with the speakers during a live Q&A session. \nJoin the webinar:https://infineon.webex.com/infineon/j.php?MTID=m86ed1962316e3106cf041e32852b7f2f
URL:https://czechsemiconductorcentre.cz/event/all2gan-insights-driving-greener-power-electronics/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/shutterstock_2550090433-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260615
DTEND;VALUE=DATE:20260618
DTSTAMP:20260923T145112
CREATED:20260602T070546Z
LAST-MODIFIED:20260604T101214Z
UID:2431-1781481600-1781740799@czechsemiconductorcentre.cz
SUMMARY:20th Silicon Saxony Days
DESCRIPTION:The Czech Semiconductor Centre will be part of this year’s Silicon Saxony Days\, one of Europe’s key high-tech and semiconductor networking events\, bringing together industry\, research\, start-ups and policy leaders from across the European ecosystem. We are pleased to highlight the participation of Petr Kamenický\, the new Director of Czech Semiconductor Centre\, with his talk: Accelerating Semiconductor Innovation in Europe: AI\, Energy and Open Architectures. His contribution on June 16 will underline the Czech Semiconductor Centre’s role in strengthening Czechia’s position within the European semiconductor landscape and supporting closer cooperation across European innovation ecosystems. This talk presents how the Czech semiconductor ecosystem – through the CSC and Czech National Semiconductor Cluster – accelerates innovation in AI hardware\, energy-efficient semiconductors and open architectures such as RISC-V\, strengthening Europe’s semiconductor value chain. \nThe programme will also feature Jana Drbohlavová\, Deputy Director of the Czech Semiconductor Centre\, who will join the panel discussion: Common challenges\, common goals: European Semiconductor Initiatives on Monday\, June 15 with Pierre Chastanet from European Commission. \n \nWe look forward to connecting with partners\, innovators and decision-makers in Dresden and contributing to the discussion on how Europe can accelerate semiconductor innovation through collaboration\, open architectures\, AI and energy-aware technologies. See you at Silicon Saxony Days 2026. \nMore details here.
URL:https://czechsemiconductorcentre.cz/event/20th-silicon-saxony-days/
LOCATION:Dresden\, Germany\, Dresden\, Germany
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Snimek-obrazovky-2026-06-02-090521.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260616
DTEND;VALUE=DATE:20260620
DTSTAMP:20260923T145112
CREATED:20260313T110551Z
LAST-MODIFIED:20260313T110749Z
UID:2110-1781568000-1781913599@czechsemiconductorcentre.cz
SUMMARY:EPoSS Annual Forum 2026
DESCRIPTION:The EPoSS Annual Forum 2026 will take place from June 16-19 in Braga\, Portugal\, kindly hosted by the EPoSS member INL. \nThe Annual Forum offers sessions with high-ranking representatives from the EU\, local authorities\, institutions and companies\, thematic sessions\, poster presentations\, start-up award pitch and award ceremony\, on-site visits to thematically relevant institutions as well as time for exchange and idea development. \nBringing together key stakeholders from across Europe\, the forum will offer a rich and dynamic programme\, including: \n\nSessions with high-ranking representatives from the European Union\, local authorities\, research institutions\, and industry;\nThematic sessions addressing strategic and emerging topics in smart systems integration;\nPoster presentations showcasing cutting-edge research and innovation;\nA start-up award pitch session\, followed by the award ceremony.\n\nThe event will provide a unique platform to connect policy\, research\, and industry within one of Portugal’s leading innovation hubs\, fostering dialogue and collaboration around the future of smart systems integration.
URL:https://czechsemiconductorcentre.cz/event/eposs-annual-forum-2026/
LOCATION:INL – International Iberian Nanotechnology Laboratory\, Av. Mte. José Veiga s/n\, Braga\, 4715-330\, Portugal
CATEGORIES:External Event
ATTACH;FMTTYPE=image/png:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/03/EPOSS2026_General-scaled-1.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260618T140000
DTEND;TZID=Europe/Prague:20260618T170000
DTSTAMP:20260923T145112
CREATED:20260529T093358Z
LAST-MODIFIED:20260529T093430Z
UID:2421-1781791200-1781802000@czechsemiconductorcentre.cz
SUMMARY:Info Session on the Chips 2026 Calls on Skills
DESCRIPTION:Responding to the growing semiconductor skills shortage in Europe and the objectives of the European Chips Act\, the Chips Joint Undertaking is launching three dedicated Skills-related Calls in July 2026 to support ambitious initiatives in semiconductor education\, training\, re-skilling\, up-skilling and talent development across the European ecosystem. \nTo help the community better understand these upcoming opportunities and prepare future collaborations\, the Chips JU Office\, in cooperation with AENEAS\, EPoSS and INSIDE is organising the Info Session on the Chips JU 2026 Calls on Skills. \nAgenda \n14:00 – 14:05 Welcome & Opening \n\nMatei Arghirescu\, Chips JU Office\nCaroline Bedran / Patrick Cogez\, AENEAS\n\nIntroduction to the Skills Calls context and Europe’s semiconductor talent challenge. \n14:05 – 15:00     Block 1: Skills Hubs of Excellence (HoE): Moderated by Patrick Cogez\, AENEAS \n\nPresentation of the Call by the Chips JU Office\nEuropean Commission perspective (Stefano Selleri\, DG CONNECT)\nNational representatives (TBD)\nCommunity project idea presentation(s)\nQ&A session\n\n15:00 – 15:05 Short Break \n15:05 – 16:00     Block 2: Pilot Federation \nSame structure- European Commission perspective (Stefano Selleri\, DG CONNECT) \n16:00 – 16:05 Short Break \n16:05 – 17:00      Block 3: Stimulation of Chip Design \nSame structure- European Commission perspective (Marco Ceccarelli\, DG CONNECT) \n17:00 – 17:05 Closing Remarks\nRegistration is free of charge and available here.
URL:https://czechsemiconductorcentre.cz/event/info-session-on-the-chips-2026-calls-on-skills/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/1779806475660.jpg
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260624
DTEND;VALUE=DATE:20260625
DTSTAMP:20260923T145112
CREATED:20260402T073253Z
LAST-MODIFIED:20260402T073253Z
UID:2180-1782259200-1782345599@czechsemiconductorcentre.cz
SUMMARY:Analog IC Design Using Open Source Tools and IHP-Open-PDK
DESCRIPTION:Date: June 24\, 2026 \nTime: 8:30 – 18:30 \nLocation: Poznan University of Technology \nParticipant limit: 15 people (first come\, first served) \nParticipation fee: 100 EUR (the price does not include VAT\, students are exempt from the fee). Registration is on a first-come\, first-served basis. \nWorkshop format: Interactive demonstration with the possibility to work at stations prepared by the organizer. Personal computers are not required; however\, participants may use their own laptops if they wish. \nAgenda:\n\n8:30 – 9:00 – Participant registration\, organizational introduction\n9:00 – 10:30 – Introduction to analog design in an open-source environment (overview of tools: Xschem\, Ngspice\, IHP-Open-PDK\, workflow basics)\n10:30 – 10:45 – Coffee break\n10:45 – 12:30 – Analog schematic design in Xschem – best practices\, parameterization\, DC\, AC\, and transient simulations (live demonstration)\n12:30 – 13:30 – Lunch break\n13:30 – 15:00 – Design of a sample analog circuit (e.g.\, StrongARM latch comparator) – operation analysis\, Monte Carlo simulations\, mismatch analysis\, parameter verification\n15:00 – 15:15 – Coffee break\n15:15 – 17:00 – Introduction to layout in KLayout\, analog design principles (matching\, symmetry\, noise minimization)\, PyCells – mask design automation\n17:00 – 18:00 – Complete design flow: from schematic to verification (LVS/DRC – process overview)\, fillers\, chip finishing\, sign-off\n18:00 – 18:30 – Q&A session\, workshop summary\n\nTechnical Scope\n\nFundamentals of CMOS analog circuit design\nWorking with open-source tools in a design environment\nElectrical simulations and interpretation of results\nIntroduction to analog layout and good design practices\nOverview of the complete design flow (schematic → simulation → layout → verification)\n\n 
URL:https://czechsemiconductorcentre.cz/event/analog-ic-design-using-open-source-tools-and-ihp-open-pdk/
LOCATION:Poznan\, Poznan\, Poland
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2025/04/2024-UMEL-Laborky-12-scaled.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260624T093000
DTEND;TZID=Europe/Prague:20260624T150000
DTSTAMP:20260923T145112
CREATED:20260616T070136Z
LAST-MODIFIED:20260616T070136Z
UID:2469-1782293400-1782313200@czechsemiconductorcentre.cz
SUMMARY:Digital Europe Program Online National Information Day
DESCRIPTION:Funding for AI\, cybersecurity\, advanced digital skills\, and European data infrastructure for 2026 is now open\, and we’ll show you how to get involved—all in one place. \nCzechInvest and the Ministry of Industry and Trade invite you to the Digital Europe Program Online National Information Day\, which will take place on Wednesday\, June 24\, 2026\, starting at 9:30 a.m. online via the MS Teams platform. \nThe Digital Europe program provides businesses\, research organizations\, and public administration with access to cutting-edge digital technologies and European funding. At the info day\, you will learn: \n\nwhich calls are currently open and what is expected of applicants\,\nwhat the funding rules\, eligibility criteria\, and most common mistakes in applications are\,\nhow to link Digital Europe with synergies from the Horizon Europe program\,\nand how the European network of national contact points DEP4ALL can help you with your preparation.\n\nSpeakers will include Kristina Kardum\, Head of the Digital Europe Program Sector at the European Commission (her presentation will be in English)\, along with experts from CzechInvest\, NÚKIB\, and the Prague Technology Center. \nThe event is intended for companies\, research organizations\, and public administration bodies considering submitting an application to the Digital Europe program: whether you have a specific project proposal or are just considering whether the program is right for you. The current calls for proposals close in early October. Since the summer significantly shortens the effective time for preparation\, it pays to start looking for partners and building a consortium right now\, as a high-quality international project cannot be put together in just a few weeks. \nA follow-up opportunity to find project partners: immediately after the info day\, on the same day from 1:00 PM to 3:00 PM\, the DEP Online Matchmaking Event (in English) will take place\, focused on partnerships for the current (10th) call of the Digital Europe Program. You can look forward to a presentation of partner search tools (the b2match platform)\, thematic breakout sessions on the calls\, short participant pitches\, and networking. \nParticipation is free after registration. Please register for both events HERE: we will send you the access link to MS Teams via email before the event. The program is subject to minor changes.
URL:https://czechsemiconductorcentre.cz/event/digital-europe-program-online-national-information-day/
LOCATION:on-line on Teams
CATEGORIES:External Event
ATTACH;FMTTYPE=image/jpeg:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/06/Logo_Digitalni_Evropa.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=Europe/Prague:20260629T130000
DTEND;TZID=Europe/Prague:20260629T143000
DTSTAMP:20260923T145112
CREATED:20260529T092510Z
LAST-MODIFIED:20260529T092657Z
UID:2417-1782738000-1782743400@czechsemiconductorcentre.cz
SUMMARY:Building the Future Together: Integrating Sustainability in the Semiconductor Ecosystem
DESCRIPTION:This joint webinar by GENESIS and the European Chips Skills Academy (ECSA) explores how sustainability and workforce development can shape the semiconductor industry’s future. The session will highlight the role of PFAS in semiconductor manufacturing\, the challenges\, and how the GENESIS project is working with industry partners to identify safer and more sustainable alternatives. Participants will also gain insight into how ECSA is helping equip the next generation of semiconductor professionals with the skills needed for a more sustainable ecosystem. \nMore details about the event can be found here. \nRegistration here.
URL:https://czechsemiconductorcentre.cz/event/building-the-future-together-integrating-sustainability-in-the-semiconductor-ecosystem/
LOCATION:on-line
CATEGORIES:External Event
ATTACH;FMTTYPE=image/webp:https://czechsemiconductorcentre.cz/wp-content/uploads/2026/05/June-1.png.webp
END:VEVENT
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