A new pilot IP Block Catalogue developed by the Czech National Semiconductor Cluster (CNSC) within its activities in the Czech Semiconductor Centre is making reusable semiconductor design IP easier to discover and access. The tool creates a structured route from an initial design need to a technically reviewed IP block, its provider and, where relevant, further European services available through EuroCDP and the Chips for Europe pilot lines.
For start-ups, SMEs and research teams developing a new chip, finding the right intellectual property can be almost as important as developing the design itself. Reusing an existing and validated IP block can significantly shorten the development process, but identifying suitable technology, understanding its maturity and technical parameters, and finding the right licensing contact can be difficult. The pilot IP Block Catalogue (EUIP) has been created to address this fragmentation.
Developed by the Czech National Semiconductor Cluster (CNSC) as part of its activities within the Czech Semiconductor Centre (CSC), the catalogue acts as a practical navigation and structured brokerage tool. It brings together semiconductor design IP offered by Chips Competence Centres, research organisations, companies and other members of their ecosystems and makes it easier for potential users to identify relevant solutions.
Rather than acting simply as a public database, the catalogue is designed to provide a structured route from initial technology search to direct expert contact.
From a technical requirement to the right provider
Each IP block submitted to the catalogue is described through a standardised technical card. The information includes its intended use case, Technology Readiness Level (TRL), validation status, technology node or PDK, area, performance, power consumption and interfaces, as well as the EDA tools used, licensing regime and availability.
Submissions then undergo a technical review covering the declared use case, TRL and key parameters. Only the information required for an initial assessment is made publicly available. More detailed or sensitive technical information can subsequently be exchanged directly between the potential user and IP provider under a non-disclosure agreement.
This approach is intended to make the initial search easier without compromising the intellectual property or commercially sensitive information of the provider. The current public pilot also explicitly states that IP ownership remains with the provider and that any commercial licensing agreement is negotiated directly between the provider and the user.
A start-up, SME or research team interested in a particular block can request access through the catalogue. The Competence Centre then brokers contact with the IP owner. Where appropriate, the user can also be guided towards additional European infrastructure, including the European Chips Design Platform (EuroCDP) or a suitable Chips for Europe pilot line.
Connecting national expertise with EuroCDP
This link is particularly important as Europe builds a more integrated environment for semiconductor design. EuroCDP is being developed as a European entry point providing chip designers with access to design IP, EDA tools, expert support, fabrication, testing, training and other services. One of its central aims is to lower the technical and economic barriers faced particularly by start-ups, SMEs and research teams when moving from an idea towards a working chip.
The pilot catalogue complements this model at Competence Centre level. A company does not necessarily need to know in advance which European programme, provider or infrastructure it requires. It can start with a concrete need – for example, a particular analogue, digital, security or interface function – and use the catalogue and the Competence Centre network to identify the next step.
The catalogue currently brings together 47 IP blocks from 34 providers, including contributions linked to partner Competence Centres, EuroCDP Design Enablement Teams and five EDA/IP vendors with European framework offerings. These include Siemens EDA, which in May 2026 became the first EDA provider to sign a framework agreement with the Chips Joint Undertaking for access to its tools through EuroCDP.
From a Czech pilot to cross-border IP exchange
The next step is to test the approach across several national semiconductor ecosystems. CNSC has prepared a Cross-CCC IP Exchange Pilot together with four partner Chips Competence Centres: ChipNL in the Netherlands, SK Chips Competence Centre in Slovakia, the Swedish Chips Competence Centre and CC Chip.si in Slovenia.
Under the proposed model, each centre will contribute IP entries from its national ecosystem and broker requests between participating communities on a reciprocal basis. Clear referral and KPI attribution rules are also being introduced to ensure that cross-border support is recorded consistently without double counting. A pilot Cooperation Note is prepared for signature in Q4 2026.
This cross-border dimension reflects the wider role of Chips Competence Centres: local expertise should provide an accessible gateway to European capabilities rather than stop at national borders.
Making existing technology easier to use
Europe already has considerable semiconductor design expertise distributed across companies, universities, research organisations, design houses and technology providers. The challenge is often not whether the expertise exists, but whether a company can find it and access it efficiently.
The pilot IP Block Catalogue addresses precisely this gap. By combining structured technical information, expert review and brokerage between users and providers, it can make reusable design IP more visible while creating a clearer path towards the wider services of EuroCDP and the European semiconductor infrastructure.
For start-ups and SMEs in particular, this means a simpler starting point: define the design need, identify a suitable IP block and let the Competence Centre help navigate the next steps towards expertise, licensing and, ultimately, prototyping.
